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    A FREQUENCY DIVIDER CIRCUIT AND A FREQUENCY SYNTHESIZER CIRCUIT
    1.
    发明公开
    A FREQUENCY DIVIDER CIRCUIT AND A FREQUENCY SYNTHESIZER CIRCUIT 审中-公开
    一个分频器电路和一个频率合成器电路

    公开(公告)号：EP3242402A1

    公开(公告)日：2017-11-08

    申请号：EP17166520.1

    申请日：2017-04-13

    申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

    发明人： XUE, Pandou ,  FENG, Guangtao

    IPC分类号： H03K21/10 ,  H03K21/02

    CPC分类号： H03L7/18 ,  H03K3/356113 ,  H03K21/026 ,  H03K21/10

    摘要： Afrequency divider circuit and a frequency synthesizer circuit are presented, comprising:
    first and second flip-flops;
    a phase inverter, wherein an output electrode of the first flip-flop is connected to an input electrode of the second flip-flop and an output electrode of the phase inverter, an output electrode of the second flip-flop is connected to an input electrode of the phase inverter and an input electrode of the first flip-flop, a control electrode of the phase inverter is connected to a control signal; and
    a control module, wherein the first flip-flop is connected to a voltage source through the control module, the control module is connected to the control signal and controls the connection between the first flip-flop and the voltage source. When the control signal is a first-mode signal, the first flip-flop is disconnected from the voltage source, providing a functionality of a N-division frequency divider. When both the control signal and an output signal of the second flip-flop are a second-mode signal, a functionality of a N+1-division frequency divider is provided.

    摘要翻译： 提供了频率分频器电路和频率合成器电路，包括：第一和第二触发器; 反相器，其中第一触发器的输出电极连接到第二触发器的输入电极和反相器的输出电极，第二触发器的输出电极连接到输入电极 所述反相器的控制电极与所述第一触发器的输入电极连接，所述反相器的控制电极与控制信号连接; 以及控制模块，其中第一触发器通过控制模块连接到电压源，控制模块连接到控制信号并控制第一触发器和电压源之间的连接。 当控制信号是第一模式信号时，第一触发器从电压源断开，提供N分频分频器的功能。 当第二触发器的控制信号和输出信号都是第二模式信号时，提供N + 1分频分频器的功能。

    CIRCUIT FOR SHIFT OPERATION AND ARRAY CIRCUIT
    2.
    发明公开
    CIRCUIT FOR SHIFT OPERATION AND ARRAY CIRCUIT 审中-公开
    移位电路和阵列电路

    公开(公告)号：EP3188191A1

    公开(公告)日：2017-07-05

    申请号：EP14903436.5

    申请日：2014-09-30

    申请人： Huawei Technologies Co. Ltd.

    发明人： HE, Rui ,  XU, Ronggang ,  ZHAO, Junfeng

    IPC分类号： G11C19/28

    CPC分类号： G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C14/009 ,  G11C19/28 ,  G11C19/287 ,  G11C2013/0073 ,  H03K3/356104 ,  H03K3/356113 ,  H03K3/356121

    摘要： A circuit and an array circuit for implementing a shift operation are provided. The circuit for implementing a shift operation includes a resistive random-access memory and four switches, where a first switch is closed when a first end of the first switch is at a low level, a fourth switch is closed when a first end of the fourth switch is at a low level, a second switch is closed when a first end of the second switch is at a high level, and a third switch is closed when a first end of the third switch is at a high level; a second end of the first switch and a second end of the third switch are connected to a negative input end of the resistive random-access memory; a second end of the second switch and a second end of the fourth switch are connected to a positive input end of the resistive random-access memory; the first end of the first switch, the first end of the second switch, the first end of the third switch, and the first end of the fourth switch are connected to an output end of a previous-stage circuit for implementing a shift operation; a third end of the first switch and a third end of the second switch are connected to a bias voltage end; and a third end of the third switch and a third end of the fourth switch are connected to a ground end. The shift circuit has a simple structure and can improve computational efficiency.

    摘要翻译： 提供了用于实现移位操作的电路和阵列电路。 用于实现移位操作的电路包括电阻随机存取存储器和四个开关，其中当第一开关的第一端处于低电平时第一开关闭合，当第四开关的第一端闭合时第四开关闭合 开关处于低电平，当第二开关的第一端处于高电平时，第二开关闭合，并且当第三开关的第一端处于高电平时，第三开关闭合; 所述第一开关的第二端和所述第三开关的第二端连接所述电阻式随机存取存储器的负输入端; 所述第二开关的第二端和所述第四开关的第二端连接所述电阻式随机存取存储器的正输入端; 所述第一开关的第一端，所述第二开关的第一端，所述第三开关的第一端和所述第四开关的第一端连接到用于实现移位操作的前一级电路的输出端; 所述第一开关的第三端和所述第二开关的第三端连接到偏置电压端; 并且第三开关的第三端和第四开关的第三端连接到接地端。 移位电路结构简单，可以提高计算效率。

    Latch circuit and display device
    5.
    发明公开
    Latch circuit and display device 审中-公开
    阻断电路和显示装置

    公开(公告)号：EP2584700A3

    公开(公告)日：2014-06-04

    申请号：EP12188809.3

    申请日：2012-10-17

    申请人： Pixtronix, Inc.

    发明人： Miyazawa, Toshio ,  Akimoto, Hajime

    IPC分类号： G09G3/36 ,  H03K3/356

    CPC分类号： H03K5/153 ,  G09G3/2092 ,  G09G3/3433 ,  G09G2310/02 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2310/08 ,  G09G2320/045 ,  H03K3/356113 ,  H03K2005/00078 ,  H03K2005/00215

    摘要： A latch circuit which can control a drain avalanche effect and improve reliability is provided. The latch circuit includes an input transistor (NMT1) importing a voltage corresponding to"0" or "1" when the scanning voltage (φG) is input to a gate, a storage capacitance (CD) storing a voltage imported by the input transistor (NMT1), and having a first electrode and a second electrode, the first electrode is input with a capacitance control signal (φW) and the second electrode is connected to a second electrode (N1) of the input transistor (NMT1), a first conduction type first transistor (NMT2) having a gate connected to the second electrode (N1) of the input transistor (NMT1), a second electrode (N2) connected to a first output terminal (OUT1), and a first electrode input with a first latch control signal (φAC1), and a second conduction type second transistor (PMT3) having a gate connected to the second electrode (N2) of the first transistor (NMT2), a second electrode (N3) connected to a second output terminal (OUT2), and a first electrode input with a second latch control signal (φAC2).

    LEVEL SHIFTER FOR DIFFERENTIAL SIGNALS WITH BALANCED TRANSITION TIMES
    6.
    发明公开
    LEVEL SHIFTER FOR DIFFERENTIAL SIGNALS WITH BALANCED TRANSITION TIMES 有权
    层滑动形成平衡过渡时代的差分信号

    公开(公告)号：EP2564505A1

    公开(公告)日：2013-03-06

    申请号：EP11717416.9

    申请日：2011-04-18

    申请人： Qualcomm Incorporated

    发明人： SRIVASTAVA, Ankit ,  QUAN, Xiaohong

    IPC分类号： H03K3/356 ,  H03K19/003 ,  H03K5/151 ,  H03K5/00

    CPC分类号： H03K3/356113 ,  H03K5/151 ,  H03K19/00323 ,  H03K2005/00136

    摘要： A level shifter (400) and method are provided for balancing rise and fall times of a signal. An input circuit (420, 413) receives a differential logic signal (Inp, Inn) with two complimentary logic levels. A level transition balancing circuit (420) balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element (430) stores and provides outputs (outp, ounn) of the level shifted versions of the logic levels. The level transition balancing circuit (420) includes a capacitor (421) in parallel with a field-effect transistor (422) for each input. The capacitor destabilizes inputs to the logic element and balances the transition using the capacitance and a level (435, 436) previously stored in the logic element.

    Level shifter having low duty cycle distorsion
    7.
    发明公开
    Level shifter having low duty cycle distorsion 审中-公开
    Pegelumsetzer mit NiedrigerTastverhältnisverzerrung

    公开(公告)号：EP2214314A3

    公开(公告)日：2010-08-11

    申请号：EP10004835.4

    申请日：2008-06-25

    申请人： Qualcomm Incorporated

    发明人： Lee, Chulkyu

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356113

    摘要： A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal onto a first input of the level shifting latch and supplies an inverted version of the input signal onto a second input of the level shifting latch. A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.

    摘要翻译： 电平移位器包括反相电路，交叉耦合电平移位锁存器和SR逻辑门锁存器。 电平移位锁存器的第一和第二输出耦合到SR锁存器的组合（S）和复位（R）输入。 由第一电源电压VDDL供电的反相电路将输入信号的非反相版本提供到电平移位锁存器的第一输入端，并将输入信号的反相形式提供给电平移位锁存器的第二输入端。 输入信号的低电平至高电平跳变使SR锁存器复位，而高电平至低电平转换则设置SR锁存器。 电平转换器的占空比失真偏移在电压，过程和温度转角上小于50皮秒，电平转换器的电源电压裕度大于VDDL额定值的四分之一。

    LEVEL SHIFTER HAVING LOW DUTY CYCLE DISTORTION
    8.
    发明公开
    LEVEL SHIFTER HAVING LOW DUTY CYCLE DISTORTION 有权
    具有低占空比失真电平变换器

    公开(公告)号：EP2181503A1

    公开(公告)日：2010-05-05

    申请号：EP08771964.7

    申请日：2008-06-25

    申请人： QUALCOMM Incorporated

    发明人： LEE, Chulkyu

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356113

    摘要： A level shifter (100) includes an inverting circuit (104), a cross-coupled level shifting latch (102), and a SR logic gate latch (103). The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal (IND) onto a first input of the level shifting latch (112) and supplies an inverted version of the input signal (INB) onto a second input of the level shifting latch (113). A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.

    SEMICONDUCTOR DEVICE AND LEVEL SHIFTING CIRCUIT
    10.
    发明公开
    SEMICONDUCTOR DEVICE AND LEVEL SHIFTING CIRCUIT 审中-公开
    半导体器件和电平转换电路

    公开(公告)号：EP1833168A4

    公开(公告)日：2008-08-20

    申请号：EP05822388

    申请日：2005-12-27

    申请人： UCHIDA YASUHISA

    发明人： UCHIDA YASUHISA

    IPC分类号： H03M1/76 ,  H03K19/0185

    CPC分类号： H03M1/76 ,  H03K3/356113 ,  H03K17/693

    摘要： A semiconductor device by which chip size increase is suppressed even the number of bits is increased. In a high withstand voltage digital/analog converter (1), a voltage generated between a potential (VH) and a potential (VL) is divided, and one of a plurality of potentials (3-9) generated by the division based on input signals (D0 to DN-1) can be outputted. The high withstand voltage digital/analog converter is provided with a plurality of element groups (11, 13); an output element group (15); and a level shifting section (17) which shifts the level of the potential of the input signal to a potential required for operating each of the output element group (15) and element groups (11, 13) and applies the potential. The potentials (3-9) are classified into a plurality of groups by potential level order, a voltage between group potentials, which correspond by being provided for each group, is applied to each of element groups (11, 13), and each element group operate, and based on the input signal, the element group outputs one of the potentials in the corresponding group. A voltage between the potential (VH) and the potential (VL) is applied to the output element group (15), and the output element group operates, and based on the input signal, the output element group outputs one of the potentials which can be outputted by the element groups (11, 13).