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26 条记录 (耗时 0.012 秒)

    SPLIT GATE NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE, WORD LINE, ERASE GATE
    12.
    发明公开
    SPLIT GATE NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE, WORD LINE, ERASE GATE 审中-公开
    分离门非易失性存储器单元具有浮动栅极，字线，擦除栅极

    公开(公告)号：EP3320561A1

    公开(公告)日：2018-05-16

    申请号：EP16741416.8

    申请日：2016-06-17

    申请人： Silicon Storage Technology Inc.

    发明人： YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  TADAYONI, Mandana ,  SU, Chien-Sheng ,  DO, Nhan

    IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

    摘要： A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.

    INTEGRATION OF SPLIT GATE FLASH MEMORY ARRAY AND LOGIC DEVICES
    13.
    发明公开
    INTEGRATION OF SPLIT GATE FLASH MEMORY ARRAY AND LOGIC DEVICES 审中-公开
    分裂栅极闪存阵列与逻辑器件的集成

    公开(公告)号：EP3266039A1

    公开(公告)日：2018-01-10

    申请号：EP16711425.5

    申请日：2016-03-02

    申请人： Silicon Storage Technology Inc.

    发明人： CHEN, Chung-Ming ,  YANG, Jeng-Wei ,  SU, Chien-Sheng ,  WU, Man-Tang ,  DO, Nhan

    IPC分类号： H01L21/28 ,  G11C16/04 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

    摘要： A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

    DOUBLE PATTERNING METHOD OF FORMING SEMICONDUCTOR ACTIVE AREAS AND ISOLATION REGIONS
    19.
    发明授权
    DOUBLE PATTERNING METHOD OF FORMING SEMICONDUCTOR ACTIVE AREAS AND ISOLATION REGIONS 有权

    公开(公告)号：EP3097581B1

    公开(公告)日：2018-09-19

    申请号：EP14822025.4

    申请日：2014-12-16

    申请人： Silicon Storage Technology Inc.

    发明人： YANG, Jeng-Wei ,  SU, Chien-Sheng

    IPC分类号： H01L21/762 ,  H01L21/308

    CPC分类号： H01L21/76224 ,  H01L21/3086 ,  H01L21/3088

    摘要： A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.

    DOUBLE PATTERNING METHOD OF FORMING SEMICONDUCTOR ACTIVE AREAS AND ISOLATION REGIONS
    20.
    发明公开
    DOUBLE PATTERNING METHOD OF FORMING SEMICONDUCTOR ACTIVE AREAS AND ISOLATION REGIONS 审中-公开
    双筛选方法，成型有源半导体区和隔离区

    公开(公告)号：EP3097581A1

    公开(公告)日：2016-11-30

    申请号：EP14822025.4

    申请日：2014-12-16

    申请人： Silicon Storage Technology Inc.

    发明人： YANG, Jeng-Wei ,  SU, Chien-Sheng

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224 ,  H01L21/3086 ,  H01L21/3088

    摘要： A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.