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    HARDWARE DATA COMPRESSOR THAT DIRECTLY HUFFMAN ENCODES OUTPUT TOKENS FROM LZ77 ENGINE
    11.
    发明公开
    HARDWARE DATA COMPRESSOR THAT DIRECTLY HUFFMAN ENCODES OUTPUT TOKENS FROM LZ77 ENGINE 审中-公开
    硬质合金麻醉剂麻醉师DIREKTER HUFFMAN-CODIERUNG VON AUSGABE-TOKEN VON LZ77-发动机

    公开(公告)号：EP3093999A1

    公开(公告)日：2016-11-16

    申请号：EP15195312.2

    申请日：2015-11-19

    申请人： VIA Alliance Semiconductor Co., Ltd.

    发明人： HENRY, G Glenn ,  PARKS, Terry

    IPC分类号： H03M7/30 ,  H03M7/40

    CPC分类号： H03M7/42 ,  G11C15/04 ,  H03M7/3086 ,  H03M7/40 ,  H03M7/4031 ,  H03M7/6058

    摘要： A hardware data compressor. An LZ77 compression engine scans an input block of characters and produces tokens, the tokens are either literal characters of the input block or a back pointer to replaced strings of characters of the input block. A Huffman encoding engine receives the tokens produced by the LZ77 compression engine and Huffman encodes the tokens using a Huffman code table to generate a compressed output block. The hardware data compressor is without a memory to intermediately store the back pointers and instead, for each token produced by the LZ77 engine, the Huffman encoding engine directly receives the token from the LZ77 engine and outputs Huffman codes corresponding in the Huffman code table to respective symbols associated with the token before the LZ77 engine produces the next token.

    摘要翻译： 硬件数据压缩器。 LZ77压缩引擎​​扫描输入的字符块并产生令牌，令牌是输入块的文字字符或用于替换输入块字符串的后退指针。 霍夫曼编码引擎接收由LZ77压缩引擎​​产生的令牌，霍夫曼使用霍夫曼代码表对令牌进行编码以生成压缩输出块。 硬件数据压缩器没有存储器来中间存储后向指针，而是对于由LZ77引擎产生的每个令牌，霍夫曼编码引擎直接从LZ77引擎接收令牌，并将霍夫曼代码表中对应的霍夫曼代码输出到相应的 在LZ77引擎产生下一个令牌之前与令牌相关联的符号。

    CACHE REPLACEMENT POLICY THAT CONSIDERS MEMORY ACCESS TYPE
    12.
    发明公开
    CACHE REPLACEMENT POLICY THAT CONSIDERS MEMORY ACCESS TYPE 审中-公开
    RICHTLINIENFÜRCACHEERSATZ UNTERBERÜCKSICHTIGUNGDES SPEICHERZUGRIFFTYPS

    公开(公告)号：EP3055775A1

    公开(公告)日：2016-08-17

    申请号：EP14891609.1

    申请日：2014-12-14

    申请人： VIA Alliance Semiconductor Co., Ltd.

    发明人： HOOKER, Rodney, E. ,  EDDY, Colin ,  REED, Douglas, R. ,  GREER, John, Michael ,  PARKS, Terry

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0864 ,  G06F8/4442 ,  G06F12/08 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/123 ,  G06F12/126 ,  G06F12/127 ,  G06F2212/1021 ,  G06F2212/604

    摘要： An associative cache memory (102), comprising: an array (104) of storage elements (112) arranged as M sets by N ways; an allocation unit (106) allocates the storage elements (112) in response to memory accesses (122) that miss in the cache memory (102). Each memory access (122) selects a set. Each memory access (122) has an associated memory access type (MAT) (101) of a plurality of predetermined MATs (101). Each valid storage element (112) has an associated MAT (101); a mapping (108) that includes, for each MAT (101), a MAT priority (3277). In response to a memory access (122) that misses in the array (104), the allocation unit (106): determines a most eligible way and a second most eligible way of the selected set for replacement based on a replacement policy; and replaces the second most eligible way rather than the most eligible way when the MAT priority (3277) of the most eligible way is greater than the MAT priority (3277) of the second most eligible way.

    摘要翻译： 一种联想高速缓冲存储器，包括：通过N路布置成M组的存储元件的阵列; 分配单元响应于错过高速缓存存储器的存储器访问来分配存储元件。 每个存储器访问选择一个集合。 每个存储器访问具有多个预定MAT的相关联的存储器访问类型（MAT）。 每个有效存储元件都有一个相关的MAT; 对于每个MAT，包括MAT优先级的映射。 响应于在阵列中遗漏的存储器访问，分配单元：基于替换策略来确定所选择的集合的最符合资格的方式和最符合条件的方式来进行替换; 并且最符合条件的方法的MAT优先级大于第二最合格方式的MAT优先级时，替代第二最符合条件的方式而不是最符合条件的方式。

    CONVERSION SYSTEM FOR A PROCESSOR WITH AN EXPANDABLE INSTRUCTION SET ARCHITECTURE FOR DYNAMICALLY CONFIGURING EXECUTION RESOURCES
    18.
    发明公开
    CONVERSION SYSTEM FOR A PROCESSOR WITH AN EXPANDABLE INSTRUCTION SET ARCHITECTURE FOR DYNAMICALLY CONFIGURING EXECUTION RESOURCES 审中-公开
    具有可扩展指令集架构的处理器的转换系统，用于动态配置执行资源

    公开(公告)号：EP3316130A1

    公开(公告)日：2018-05-02

    申请号：EP16207539.4

    申请日：2016-12-30

    申请人： VIA Alliance Semiconductor Co., Ltd.

    发明人： HENRY, G Glenn ,  HOOKER, Rodney E ,  PARKS, Terry ,  REED, Douglas R

    IPC分类号： G06F9/45 ,  G06F15/78

    CPC分类号： G06F8/41 ,  G06F8/443 ,  G06F8/4441 ,  G06F8/52 ,  G06F15/7867 ,  G06F15/7871 ,  G06F15/7892

    摘要： A conversion system that converts a standard executable program according to a predetermined ISA into a custom executable program executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The conversion system includes a PEU programming tool that converts a functional description of a processing operation to be performed by the PEU of the processor into programming information for the PEU to perform the processing operation in response to the UDI. A converter converts the standard executable program into the custom executable program and includes an optimization routine that replaces a portion of the standard executable program with the specified UDI and that inserts the UDI into the custom executable program, and that further inserts a UDI load instruction that specifies the UDI and a location of the programming information in the custom executable program.

    摘要翻译： 一种转换系统，其根据预定的ISA将标准可执行程序转换为可由通用处理器执行的定制可执行程序。 处理器包括一个可编程执行UDI的PEU。 转换系统包括PEU编程工具，其将要由处理器的PEU执行的处理操作的功能描述转换为用于PEU响应于UDI执行处理操作的编程信息。 转换器将标准可执行程序转换为自定义可执行程序，并包含一个优化例程，该程序用指定的UDI替换标准可执行程序的一部分，并将UDI插入到自定义可执行程序中，并进一步插入UDI加载指令 指定UDI和编程信息在自定义可执行程序中的位置。

    PROCESSOR WITH PROGRAMMABLE PREFETCHER
    19.
    发明公开
    PROCESSOR WITH PROGRAMMABLE PREFETCHER 审中-公开
    具有可编程预置器的处理器

    公开(公告)号：EP3179375A1

    公开(公告)日：2017-06-14

    申请号：EP16203050.6

    申请日：2016-12-08

    申请人： VIA Alliance Semiconductor Co., Ltd.

    发明人： HENRY, G Glenn ,  HOOKER, Rodney E ,  PARKS, Terry ,  REED, Douglas R

    IPC分类号： G06F12/0862 ,  G06F15/78

    摘要： A processor including a programmable prefetcher for prefetching information from an external memory. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks load requests issued by the processor to retrieve information from the external memory. The programmable prefetch engine is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, such that during operation of the processor, the programmed prefetcher generates at least one prefetch address based on the load requests issued by the processor. The requester uses each generated prefetch address to prefetch information from the external memory. A prefetch memory may store one or more prefetch programs and a prefetch programmer may be included to select from among stored prefetch programs to program the prefetcher based on an executing process. Each prefetch program may be configured according to a prefetch definition.

    摘要翻译： 包含可编程预取器的处理器，用于预取来自外部存储器的信息。 可编程预取器包括负载监视器，可编程预取引擎和预取请求器。 负载监视器跟踪处理器发出的加载请求，以从外部存储器中检索信息。 可编程预取引擎被配置为由至少一个预取程序编程以作为编程预取器来操作，使得在处理器的操作期间，编程预取器基于由处理器发出的加载请求来生成至少一个预取地址。 请求者使用每个生成的预取地址来预取来自外部存储器的信息。 预取存储器可以存储一个或多个预取程序，并且可以包括预取编程器以从存储的预取程序中进行选择以基于执行过程对预取器进行编程。 每个预取程序可以根据预取定义来配置。

    PROCESSOR WITH AN EXPANDABLE INSTRUCTION SET ARCHITECTURE FOR DYNAMICALLY CONFIGURING EXECUTION RESOURCES
    20.
    发明公开
    PROCESSOR WITH AN EXPANDABLE INSTRUCTION SET ARCHITECTURE FOR DYNAMICALLY CONFIGURING EXECUTION RESOURCES 审中-公开
    可扩展指令集架构执行资源的动态配置处理器

    公开(公告)号：EP3179362A1

    公开(公告)日：2017-06-14

    申请号：EP16203047.2

    申请日：2016-12-08

    申请人： VIA Alliance Semiconductor Co., Ltd.

    发明人： HENRY, G Glenn ,  HOOKER, Rodney E ,  PARKS, Terry ,  REED, Douglas R

    IPC分类号： G06F9/30 ,  G06F15/78 ,  G06F9/22 ,  G06F9/28 ,  G06F9/45

    CPC分类号： G06F9/3016 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  G06F8/41 ,  G06F8/443 ,  G06F8/447 ,  G06F9/22 ,  G06F9/28 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3836

    摘要： A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.

    摘要翻译： 与处理器在可膨胀的指令集架构用于动态配置的执行资源。 该处理器包括一个可编程执行单元（PEU）也可以被编程为响应于用户定义指令（UDI）执行用户定义的函数。 所述PEU包括可编程逻辑元件和可编程互连器没有被共同编程以执行至少一个处理操作。 甲UDI加载器是响应于UDI加载指令没有指定UDI和编程信息的位置也被用来将PEU编程。 该PEU可以被编程为一个或多个过程的一个或多个UDIS。 指令表存储每个UDI和相应的信息以识别UDI和可能重新编程PEU如果是必要的。 甲UDI处理程序咨询指令表来识别所接收的UDI，并发送相应的信息到PEU执行对应的用户定义函数。