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    HYBRID MEMORY MANAGEMENT
    2.
    发明公开
    HYBRID MEMORY MANAGEMENT 审中-公开
    混合内存管理

    公开(公告)号：EP3291097A2

    公开(公告)日：2018-03-07

    申请号：EP17185832.7

    申请日：2017-08-11

    申请人： Google LLC

    发明人： Coburn, Joel Dylan ,  Borchers, Albert ,  Johnson, Christopher Lyle ,  Sprinkle, Robert S.

    IPC分类号： G06F12/0802 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/0868 ,  G06F12/0831

    CPC分类号： G06F3/0685 ,  G06F3/0619 ,  G06F3/065 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0835 ,  G06F12/0868 ,  G06F12/1009 ,  G06F12/1081 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/621 ,  Y02D10/13

    摘要： Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.

    摘要翻译： 用于基于利用至少一个页面表漫游器扫描页面表来确定是否为页表的每个页表项设置访问位的方法，系统和装置，所述访问位指示与页面关联的页面 表条目在最后一个扫描周期被访问; 响应于确定为与所述页面相关联的页面表条目设置了访问位，递增每个页面的计数; 在确定是否为每个页表条目设置访问位之后重置访问位; 从主存储器接收访问第一页数据的请求; 基于确定第一页数据未存储在主存储器中来启动页面错误; 并用DMA引擎来处理页面错误。

    CACHE DATA DETERMINATION METHOD AND DEVICE
    3.
    发明公开
    CACHE DATA DETERMINATION METHOD AND DEVICE 审中-公开
    缓存数据确定方法和装置

    公开(公告)号：EP3252609A1

    公开(公告)日：2017-12-06

    申请号：EP15884413.4

    申请日：2015-11-26

    申请人： Huawei Technologies Co. Ltd.

    发明人： CHAI, Yunpeng ,  SUN, Dongwang

    IPC分类号： G06F12/08

    CPC分类号： G06F12/121 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/60

    摘要： The present invention discloses a cache data determining method and apparatus, and pertains to the field of computer technologies. The method includes: acquiring a data identifier of read cache miss data; selecting, based on the acquired data identifier, a data identifier of to-be-determined data; recording data identifiers by groups; collecting statistics on quantities of occurrence times, in each group, of the data identifiers; and selecting target to-be-determined data according to the quantities of occurrence times, and determining the target to-be-determined data as cache miss data to be written into a cache memory. Data identifiers are recorded by groups, and after statistics on quantities of occurrence times, in each group, of the data identifiers is collected, target to-be-determined data is selected according to the quantities of occurrence times, and the target to-be-determined data is determined as cache miss data to be written into a cache memory. Because a large quantity of occurrence times can indicate that cache miss data is read for relatively many times. Therefore, good data having a large quantity of read times can be selected, so that a proportion of good data stored in the cache memory can be improved, and further, a hit rate of subsequent data reading can be improved.

    摘要翻译： 本发明公开了一种缓存数据的确定方法和装置，属于计算机技术领域。 该方法包括：获取读取缓存未命中数据的数据标识; 根据获取的数据标识选择待判断数据的数据标识; 按组记录数据标识符; 收集每组数据标识符的发生次数的统计数据; 并根据所述发生次数选择目标待确定数据，并将所述目标待确认数据确定为待写入高速缓冲存储器的高速缓存未命中数据。 数据标识符按组进行记录，统计出发生次数后，在每组中，收集数据标识符中的数据标识符，根据发生次数选择目标待确定数据，并将待处理目标 确定的数据被确定为将写入高速缓冲存储器的高速缓存缺失数据。 因为大量的发生时间可以指示高速缓存未命中数据被读取相对多次。 因此，可以选择具有大量读取次数的好数据，从而可以提高存储在高速缓冲存储器中的良好数据的比例，并且可以提高后续数据读取的命中率。

    A METHOD OF PARTITIONING A SET-ASSOCIATIVE CACHE IN A COMPUTING PLATFORM
    4.
    发明公开
    A METHOD OF PARTITIONING A SET-ASSOCIATIVE CACHE IN A COMPUTING PLATFORM 审中-公开
    计算平台中分组关联缓存的一种方法

    公开(公告)号：EP3244317A1

    公开(公告)日：2017-11-15

    申请号：EP17169438.3

    申请日：2017-05-04

    申请人： GE Aviation Systems LLC

    发明人： GOEBEL, Christopher John

    IPC分类号： G06F12/0864 ,  G06F12/0846 ,  G06F12/0855

    CPC分类号： G06F12/0864 ,  G06F12/0848 ,  G06F12/0857 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/1041 ,  G06F2212/601

    摘要： A method of partitioning a set-associative cache for a plurality of software components 40 may comprise identifying a cache height 26 equal to a number of sets in the set-associative cache 20 based on hardware specifications of a computing platform 12. The method may further comprise determining at least one component demand set 42 of the plurality of software components and dedicating a set 28 in the set-associative cache 20 for the at least one component demand set 42. The method may further comprise assembling a proportional component sequence 44 of the component demand set 42 having a sequence length equal to an integer submultiple of the cache height 26. The method may further comprise concatenating assembled proportional component sequences 44 to form a template for mapping a RAM to the dedicated sets 28 in the set-associative cache 20.

    摘要翻译： 为多个软件组件40划分组关联缓存的方法可以包括基于计算平台12的硬件规范识别与组关联缓存20中的组的数量相等的缓存高度26.该方法可以进一步 包括确定多个软件组件中的至少一个组件需求集合42并且将用于至少一个组件需求集合42的集合28专用于集合关联高速缓存器20中。该方法可以进一步包括：组装比例组件序列44 组件需求集合42具有等于高速缓存高度26的整数约数的序列长度。该方法还可以包括级联组合的比例组件序列44以形成用于将RAM映射到集合关联高速缓存20中的专用集合28的模板 。

    CACHE OPERATION IN A MULTI-THREADED PROCESSOR
    6.
    发明公开
    CACHE OPERATION IN A MULTI-THREADED PROCESSOR 审中-公开
    EINEM多线程处理器中的PUFFERSPEICHERBETRIEB

    公开(公告)号：EP3079068A1

    公开(公告)日：2016-10-12

    申请号：EP16163566.9

    申请日：2016-04-01

    申请人： Imagination Technologies Limited

    发明人： DAY, Philip

    IPC分类号： G06F12/08

    CPC分类号： G06F3/0611 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/22 ,  G06F2212/601 ,  Y02D10/13

    摘要： Cache operation in a multi-threaded processor is described. A small memory structure referred to as a way enable table is provided which stores an index to an n-way set associative cache. The way enable table comprises one entry for each entry in the n-way set associative cache and each entry in the way enable table is arranged to store a thread ID. The thread ID in an entry in the way enable table is the ID of the thread associated with a data item stored in the corresponding entry in the n-way set associative cache. Prior to reading entries from the n-way set associative cache identified by an index parameter, the ways in the cache are selective enabled based on a comparison of the current thread ID and the thread IDs stored in entries in the way enable table which are identified by the same index parameter.

    摘要翻译： 描述多线程处理器中的高速缓存操作。 提供了称为方式启用表的小型存储器结构，其将索引存储到n路组关联高速缓存。 启用表的方式包括n路集合关联高速缓存中的每个条目的一个条目，并且方式中的每个条目被安排为存储线程ID。 方式中的条目中的线程ID enable table是与存储在n路集关联高速缓存中的相应条目中的数据项相关联的线程的ID。 在从索引参数识别的n路集合关联缓存中读取条目之前，基于当前线程ID和存储在所识别的方式启用表中的条目中的线程ID的比较来选择性地启用高速缓存中的方式 由相同的索引参数。

    CROSS-PAGE PREFETCHING METHOD, DEVICE AND SYSTEM
    9.
    发明公开
    CROSS-PAGE PREFETCHING METHOD, DEVICE AND SYSTEM 审中-公开
    侧的边界预取方法以及设备和系统

    公开(公告)号：EP2993586A4

    公开(公告)日：2016-04-06

    申请号：EP14791035

    申请日：2014-04-17

    申请人： HUAWEI TECH CO LTD

    发明人： ZHANG LIXIN ,  ZHANG LIUHANG ,  HOU RUI ,  ZHANG KE

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/602 ,  G06F2212/6026 ,  G06F2212/608

    摘要： Embodiments of the present invention provide a cross-page prefetching method, apparatus, and system, which can improve a prefetching hit ratio of a prefetching device, and further improve efficiency of memory access. The method includes: receiving an indication message, sent by a cache, that a physical address is missing, where the indication message carries a mapped-to first physical address and contiguity information of a first physical page to which the first physical address belongs; acquiring a prefetching address according to the first physical address and a step size that is stored in a prefetching device; and if a page number of a physical page to which the prefetching address belongs is different from a page number of the first physical page, and it is determined, according to the contiguity information of the first physical page, that the first physical page is contiguous, prefetching data at the prefetching address.