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公开(公告)号：EP3284092A1
公开(公告)日：2018-02-21
申请号：EP15904934.5
申请日：2015-09-25
发明人： HU, Miao , LI, Zhiyong , STRACHAN, John Paul
IPC分类号： G11C11/16
CPC分类号： G11C13/0007 , G06G7/16 , G11C5/05 , G11C13/0023 , G11C13/003 , G11C13/0069 , G11C2213/79
摘要： A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
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公开(公告)号：EP1450289A1
公开(公告)日：2004-08-25
申请号：EP03018878.3
申请日：2003-08-19
IPC分类号： G06G7/16
CPC分类号： G06G7/16
摘要： There is disclosed a computation circuit (10), working in the modulation domain to generate a signal having phase modulation proportional to the ratio of the dividend (numerator) signal to the divisor (denominator) signal. In one embodiment, the phase modulated signal is demodulated by a phase demodulator (104) to produce a baseband quotient signal. The divisor signal maintains inverse proportional control of the modulation gain of the modulator by varying the carrier injection level, resulting in higher bandwidth and accuracy, and lower drift and offset compared to traditional analog computation techniques. In one embodiment the circuit contains all linear components, even though the division function is a non-linear function. The circuit and method operate when the input signals are analog or one or both are in the modulation domain.
摘要翻译： 公开了一种在调制域中工作的计算电路（10），以产生具有与分红（分子）信号与除数（分母）信号的比率成比例的相位调制的信号。 在一个实施例中，相位调制信号由相位解调器（104）解调以产生基带商信号。 除数信号通过改变载波注入电平来维持调制器的调制增益的反比例控制，导致与传统模拟计算技术相比更高的带宽和精度以及更低的漂移和偏移。 在一个实施例中，电路包含所有线性分量，即使分割函数是非线性函数。 当输入信号为模拟信号或者一个或两个处于调制域时，该电路和方法工作。
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公开(公告)号：EP0807898B1
公开(公告)日：2003-01-29
申请号：EP97107745.8
申请日：1997-05-12
发明人： Weber, Stephan
IPC分类号： G06G7/16
CPC分类号： G06G7/16
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15.发明授权A divider circuit arrangement and a dual branch receiver having such a divider circuit arrangement 失效除法电路装置和与该分频电路布置的双分支的接收器。
公开(公告)号：EP0315268B1
公开(公告)日：1994-03-16
申请号：EP88202427.6
申请日：1988-10-31
发明人： Chung, Kah-Seng
IPC分类号： G06G7/16
CPC分类号： G06G7/16
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公开(公告)号：EP3506266B1
公开(公告)日：2024-10-09
申请号：EP18209022.5
申请日：2018-11-28
CPC分类号： H03M1/12 , G11C13/0023 , G11C13/004 , G06G7/16 , G11C13/0026 , G11C11/54 , G11C2013/004520130101 , G11C13/0028 , G11C2213/7720130101 , G11C7/1006 , G06N3/065
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公开(公告)号：EP3284092A4
公开(公告)日：2018-04-25
申请号：EP15904934
申请日：2015-09-25
发明人： HU MIAO , LI ZHIYONG , STRACHAN JOHN PAUL
CPC分类号： G06G7/16 , G11C5/05 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/0069 , G11C2213/79
摘要： A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
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公开(公告)号：EP3262651A4
公开(公告)日：2018-03-21
申请号：EP15901108
申请日：2015-08-07
发明人： HU MIAO , STRACHAN JOHN PAUL , LI ZHIYONG , WILLIAMS STANLEY
CPC分类号： G11C13/0069 , G06G7/16 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C2213/77
摘要： A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, and a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections. Each junction comprises a resistive memory element, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
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公开(公告)号：EP2339500A3
公开(公告)日：2012-02-29
申请号：EP10195124.2
申请日：2010-12-15
申请人： Macroblock, Inc.
发明人： Shih, Fu-Yang
IPC分类号： G06G7/16
CPC分类号： G06G7/16
摘要： An analog multiplier includes a bias circuit, a level shifter, a multiplying circuit, and a current mirror. The analog multiplying circuit is used for inputting a first voltage and a second voltage, and outputting a product current. The product current is proportional to a product of the first voltage and the second voltage. The analog multiplier is implemented by a few devices, thereby having a simple architecture and being capable of being driven by a small amount of power.
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公开(公告)号：EP2012250A3
公开(公告)日：2011-10-12
申请号：EP08103649.3
申请日：2008-04-22
发明人： Hallak, Jalal
摘要： Die Erfindung betrifft einen Verfahren zum Betreiben eines Analog Dividierers, wobei ein Sägezahn- oder Dreieckssignal aus einer erste Eingangsspannung (U1) als Divisor gebildet wird, und wobei dieses Sägezahn- oder Dreieckssignal mittels eines ersten Komparators (KO1) mit einer zweiten Eingangsspannung (U2) als Dividend in der Weise verglichen wird, dass als ein erstes Vergleichssignal (SIG1 OUT ) ein pulsweitenmoduliertes Signal erzeugt wird, dessen Mittelwert als Quotienten der Division ausgegeben wird. Dabei wird das Sägezahn- oder Dreieckssignal mittels eines ersten und eines zweiten Reglers (REG1, REG2) gebildet und dem ersten Regler (REG1) die erste Eingangsspannung (U1) oder eine dazu proportionale Spannung und das Sägezahn- oder Dreieckssignal oder ein dazu proportionales Signal in der Weise zugeführt, dass der obere Spitzenwert des Sägezahn- oder Dreieckssignals der ersten Eingangsspannung nachgeregelt wird. Des Weiteren wird dem zweiten Regler (REG2) das Bezugspotenzial und das Sägezahn- oder Dreieckssignal in der Weise zugeführt, dass der untere Spitzenwert des Sägezahn- oder Dreieckssignals dem Wert des Bezugspotenzials nachgeregelt wird.
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