公开(公告)号：EP3238252A4

公开(公告)日：2017-12-27

申请号：EP14908603

申请日：2014-12-19

Applicant: HEWLETT PACKARD ENTPR DEVELOPMENT LP

Inventor： YANG JIANHUA ,  WILLIAMS STANLEY ,  ZHANG MAX ,  LI ZHIYONG

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/26 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L47/005

Abstract: A negative differential resistance (NDR) device for non-volatile memory cells in crossbar arrays is provided. Each non-volatile memory cell is situated at a crosspoint of the array. Each non-volatile memory cell comprises a switching layer in series with an NDR material containing fast diffusive atoms that are electrochemically inactive. The switching layer is positioned between two elec-trodes.

公开(公告)号：EP3257081A4

公开(公告)日：2018-02-14

申请号：EP15882205

申请日：2015-02-11

Applicant: HEWLETT PACKARD ENTPR DEVELOPMENT LP

Inventor： ZHANG MINXIAN MAX ,  SAMUELS KATHRYN ,  YANG JIANHUA JOSHUA ,  WILLIAMS R STANLEY ,  LI ZHIYONG

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/14 ,  H01L45/146

Abstract: Provided in one example is a nonvolatile memory crossbar array. The array includes a number of junctions formed by a number of row lines intersecting a number of column lines; and a resistive memory element in series with a selector at each of the junctions coupling between one of the row lines and one of the column lines. The selector may be a volatile switch including: a bottom electrode; an oxide layer disposed over the bottom electrode, the oxide layer including Cu2O; and a top electrode disposed over the oxide layer.

公开(公告)号：EP3257082A4

公开(公告)日：2018-02-07

申请号：EP15882219

申请日：2015-02-13

Applicant: HEWLETT PACKARD ENTPR DEVELOPMENT LP

Inventor： JACKSON WARREN ,  YANG JIANHUA ,  KIM KYUNG MIN ,  LI ZHIYONG

IPC: H01L27/115

CPC classification number: H01L45/147 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/73 ,  G11C2213/77 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: A multilayered memristor includes a semiconducting n-type layer, a semiconducting p-type layer, and a semiconducting intrinsic layer. The semiconducting n-type layer includes one or both of anion vacancies and metal cations. The semiconducting p-type layer includes one or both of metal cation vacancies and anions. The semiconducting intrinsic layer is coupled between the n-type layer and the p-type layer to form an electrical series connection through the n-type layer, the intrinsic layer, and the p-type layer.

公开(公告)号：EP3284092A4

公开(公告)日：2018-04-25

申请号：EP15904934

申请日：2015-09-25

Applicant: HEWLETT PACKARD ENTPR DEVELOPMENT LP

Inventor： HU MIAO ,  LI ZHIYONG ,  STRACHAN JOHN PAUL

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G06G7/16 ,  G11C5/05 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79

Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.

公开(公告)号：EP3262651A4

公开(公告)日：2018-03-21

申请号：EP15901108

申请日：2015-08-07

Applicant: HEWLETT PACKARD ENTPR DEVELOPMENT LP

Inventor： HU MIAO ,  STRACHAN JOHN PAUL ,  LI ZHIYONG ,  WILLIAMS STANLEY

IPC: G11C13/00 ,  G11C11/15

CPC classification number: G11C13/0069 ,  G06G7/16 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/77

Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, and a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections. Each junction comprises a resistive memory element, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.