公开(公告)号：EP0232641A2

公开(公告)日：1987-08-19

申请号：EP86402738.8

申请日：1986-12-10

Applicant: ITT INDUSTRIES INC.

Inventor： Morton, Steven Gregory

IPC: G06F15/06

CPC classification number: G06F11/2051 ,  G01R31/318505 ,  G06F15/8007 ,  G11C29/28

Abstract: In a cellular array processor at least two of the plurality of processors in a row cooperate together as an address generator so that large amounts of memory external to the array chip may be addressed and in addition so that an address may be generated onboard for use by the DRAM memory associated with each processor. Based on this structure, a memory with an internal organization that is 256-bits wide may be connected to 16 16-bit processors which would require 256 bits of data. In so doing, a vast number of pins are saved, that is 256 bits of data out of the memory and 256 bits of data into the processing cells by combining the processing cells and memory on the same chip. It is significant that exactly one design of a processing cell may provide both a data processing element and an address processing element. In this way, these cells are interchangeable to maximize the yield and reliability of the device. A single address from the address generator addresses the entire onboard DRAM so as to use the number of address generators required and to reduce the amount of address decode logic required as well as minimizing power dissipation in the DRAM portion of the chip.

Abstract translation: 在蜂窝阵列处理器中，一行中的多个处理器中的至少两个处理器一起协作作为地址发生器，使得可以寻址阵列芯片外部的大量存储器，并且另外地址使得地址。 可以在板上生成以供与每个处理器相关联的DRAM存储器使用。 基于这种结构，具有256位宽的内部组织的存储器可以连接到需要256位数据的16位16位处理器。 这样做，通过将处理单元和存储器组合在同一芯片上，大量的引脚被保存在存储器中的256位数据和256位数据到处理单元中。 重要的是处理单元的恰好一个设计可以提供数据处理元件和地址处理元件。 以这种方式，这些电池可以互换，以最大限度地提高装置的产量和可靠性。 来自地址发生器的单个地址解决整个板载DRAM，以便使用所需的地址发生器的数量，并且减少所需的地址解码逻辑的数量以及最小化芯片的DRAM部分的功耗。

公开(公告)号：EP0028312A1

公开(公告)日：1981-05-13

申请号：EP80105780.3

申请日：1980-09-25

Applicant: International Business Machines Corporation

Inventor： Robbins, Wayne Edward ,  Spivey, Paul Richard ,  Travis, Terence

IPC: G06F13/00

CPC classification number: G06F11/2289 ,  G06F11/006 ,  G06F11/1004 ,  G06F12/0684 ,  G11C29/12 ,  G11C29/28 ,  G11C29/40

Abstract: A data processing system includes a processor (10), base read-only store (101) and a non-volatile read/write memory (104) interconnected by a control bus (13), a data bus (19), an address bus (14) and a selection bus (18). Add-on read-only memories (106, 107) can be coupled to the busses when required to add operating features to the system. The read/write memory (104) includes a table containing a location for each possible add-on memory. Each location contains data indicating either that the related add-on memory is connected and required by the system, or is not connected, or, if connected, not required. Each add-on memory stores, in its first location, the address of that location for verification when it is accessed.

Abstract translation: 一种数据处理系统包括通过控制总线（13），数据总线（19）来解决总线互连的处理器（10），基部只读存储器（101）和非易失性读/写存储器（104） （14）和选择总线（18）。 附加只读存储器（106，107）可以要求操作功能添加到系统中时，被耦合到所述总线。读/写存储器（104）包括一个表包含用于每个可能的附加存储器中的位置。 每个位置包含数据表示是没有相关的附加存储器被连接，并通过系统所需的，或没有连接，或者，如果连接，不是必需的。 每个附加存储器存储，在其第一位置，验证位置的地址中并当它访问。

公开(公告)号：EP0907184A3

公开(公告)日：2004-10-06

申请号：EP98115819.9

申请日：1998-08-21

Applicant: Infineon Technologies AG

Inventor： Krause, Gunnar H. ,  Kiehl, Oliver

IPC: G11C29/00

CPC classification number: G11C29/28

Abstract: Testing of a multibank memory device having a plurality of memory banks which includes activating two or more of the plurality of memory banks for participation in the test; selecting at least one common memory address corresponding to a memory cell within each activated bank; simultaneously writing test data into the selected memory cell of each activated bank; simultaneously reading the test data previously written into the selected memory cell of each activated bank; and comparing the test data read from each activated bank with the test data from each other activated bank and if a match is determined to exist, then indicating a pass condition, else indicating a fail condition.

公开(公告)号：EP0617429B1

公开(公告)日：2000-10-11

申请号：EP94100993.8

申请日：1994-01-24

Applicant: NEC CORPORATION

Inventor： Matsui, Yoshinori, c/o NEC Corporation

IPC: G11C29/00

CPC classification number: G11C29/38 ,  G11C29/26 ,  G11C29/28

Abstract: A semiconductor memory device is disclosed which has a data output circuit including a first node, a second node, first and second transistors connected in series between the first node and a potential line, third and fourth transistors connected in series between the first node and the potential line, fifth and sixth transistors connected in series between the second node and the potential line, seventh and eighth transistors connected in series between the second node and the potential line, one of the first and third transistors being driven in response to a data signal read from a selected memory cell and one of the fifth and seventh transistors being driven in response to an inverted data signal of the data signal in a normal mode while turning one of the second and fourth transistor and one of the sixth and eighth transistors ON, both of the first and third transistors being driven in response to the data signal and both of the fifth and seventh transistors being driven in response to the inverted data signal while all the second, fourth, sixth and eighth transistors ON. The output circuit further includes an output logic circuit driving an output terminal to one of first and second logic levels when the first and second nods have logic levels different from each other and to a high impedance when the first and second nodes have logic levels equal to each other.

公开(公告)号：EP0886280A1

公开(公告)日：1998-12-23

申请号：EP98303802.7

申请日：1998-05-14

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： So, Jason Siucheong

IPC: G11C29/00

CPC classification number: G11C29/28 ,  G11C11/41 ,  G11C29/34 ,  G11C29/50 ,  G11C29/56

Abstract: An integrated circuit having enhanced testing capabilities and a method of testing an integrated circuit are provided. The integrated circuit preferably includes a substrate and a memory block on the substrate. The memory block preferably has a plurality of memory cells arranged in a plurality of rows and a plurality of columns within a defined area on the substrate, at least one bit line connected to each of the plurality of memory cells and defining a column, at least one word line connected to each of the plurality of memory cells and defining a row, and sense amplifying means connected to the at least one bit line for sensing a state of an addressed memory cell in at least one of the plurality of columns. The integrated circuit also includes a selectable stress tester on the substrate and connected to the memory block for selectively stress testing only portions of the memory block and not other portions so as to determine whether to accept or reject a memory block.

Abstract translation: 一种集成电路，具有增强的检测能力并且提供集成电路的测试的方法。 集成电路优选地包括基板和在基板上的存储块。 存储器块优选地具有在基片上的限定区域内的行中的多个和列排列的多个存储单元的复数，连接到每个存储单元的所述多个所述至少一个位线和限定一列中，至少， 连接到每个存储单元的多元性和一个限定行的一条字线，并读出放大连接到所述至少一个位线用于在列的多个所述至少一个感测被寻址的存储器单元的状态的装置。 因此，该集成电路包括在衬底上的可选择的应力测试器和连接到用于选择性地应力测试存储器块仅部分而不是其他部分，以便确定是否矿接受或拒绝一个存储器块中的存储器块。

公开(公告)号：EP0757837B1

公开(公告)日：1998-11-04

申请号：EP95916796.6

申请日：1995-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： DORNEY, Timothy, Dominic ,  BALISTRERI, Anthony, Michael

IPC: G11C29/00

CPC classification number: G11C29/28

Abstract: An integrated circuit memory device (21) includes plural input/output pins (30, 127 and others) and plural arrays of addressable storage cells (31-46). A set of circuits (51, 68, 70, 71-86, 90) provides access to a unique storage location in each array (31-46) through a given row and column address. A writing circuit (47, 68, 70, 71-86, 91-106, 131-146), designed for test, provides in parallel plural copies of a test data bit. The test data bit is applied through a single pin (30) and a common data-in lead (68), for storage in an addressed storage cell in each of the arrays. A readout circuit (110, 111, 112, 171, 127, 201-216, 131-146) is arranged for reading out the stored test data bit from the addressed storage cell in each of the arrays (31-46). The writing circuit, while in a block write test mode, stores the test data bit on the common data-in lead (68) in a block of address locations in each array (31-46).

公开(公告)号：EP0757837A1

公开(公告)日：1997-02-12

申请号：EP95916796.0

申请日：1995-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： DORNEY, Timothy, Dominic ,  BALISTRERI, Anthony, Michael

IPC: G11C29

CPC classification number: G11C29/28

Abstract: An integrated circuit memory device (21) includes plural input/output pins (30, 127 and others) and plural arrays of addressable storage cells (31-46). A set of circuits (51, 68, 70, 71-86, 90) provides access to a unique storage location in each array (31-46) through a given row and column address. A writing circuit (47, 68, 70, 71-86, 91-106, 131-146), designed for test, provides in parallel plural copies of a test data bit. The test data bit is applied through a single pin (30) and a common data-in lead (68), for storage in an addressed storage cell in each of the arrays. A readout circuit (110, 111, 112, 171, 127, 201-216, 131-146) is arranged for reading out the stored test data bit from the addressed storage cell in each of the arrays (31-46). The writing circuit, while in a block write test mode, stores the test data bit on the common data-in lead (68) in a block of address locations in each array (31-46).

公开(公告)号：EP0737981A2

公开(公告)日：1996-10-16

申请号：EP96630001.4

申请日：1996-01-04

Applicant: UNITED MEMORIES, INC. ,  Nippon Steel Semiconductor Corp.

Inventor： Parris, Michael C. ,  Stalnaker, H. Kent

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C29/28

Abstract: A circuit (36, 52) and method for a memory device (10), such as a synchronous dynamic random access memory (SDRAM) having at least two memory banks (14, 16). Columns of at least two memory banks (14, 16) are concurrently addressable to permit data to be written to, or read from, the at least two memory banks (14, 16) concurrently. By writing data concurrently to more than one memory bank, testing of the memory of the memory device (10) can be effectuated in a reduced period of time. Data can also be written or read from a single bank (14, 16) in a multi-bank RAM without requiring that a particular bank (14, 16) be specified during a read/write command.

Abstract translation: 一种电路（36，52）和方法，用于一个存储装置（10）：如具有至少两个存储体（14，16）同步动态随机存取存储器（SDRAM）。 至少两个存储体（14，16）的列寻址的同时，以允许数据被写入到或从所述至少两个存储体（14，16）同时读出。 通过同时将数据写入到多个存储体，所述存储器装置（10）的存储器的测试可以在减少的时间段来实现。 数据因此可以被写入或而不需要来自在多排RAM单银行（14，16）读做了特定的银行（14，16）的读/写命令期间被指定。

公开(公告)号：EP0440206B1

公开(公告)日：1996-03-27

申请号：EP91101223.5

申请日：1991-01-30

Applicant: NEC CORPORATION

Inventor： Mizukami, Takeshi

IPC: G11C29/00

CPC classification number: G11C29/12 ,  G11C29/28

公开(公告)号：EP0505603B1

公开(公告)日：1995-06-21

申请号：EP91105066.4

申请日：1991-03-28

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： Schrenk, Hartmut

IPC: G07F7/10 ,  G11C29/00

CPC classification number: G07F7/1008 ,  G06Q20/341 ,  G07F7/084 ,  G11C29/28 ,  G11C29/36 ,  G11C29/42