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11.发明公开SELF-COMPENSATING DIGITAL DELAY SEMICONDUCTOR DEVICE WITH SELECTABLE OUTPUT DELAYS AND METHOD THEREFOR. 失效具有可选择输出延迟和相关方法DIGITAL自动补偿，半导体延迟电路。
公开(公告)号：EP0626113A4
公开(公告)日：1995-02-15
申请号：EP93904876
申请日：1993-02-04
申请人： VLSI TECHNOLOGY INC
发明人： SORRELLS PETER , GERINGER NED
CPC分类号： H03L7/0805 , H03K5/131 , H03K5/135 , H03K19/00323 , H03K2005/00104 , H03L7/0814
摘要： A self-compensated digital delay semiconductor device is disclosed which uses two identical chains (10 and 12) of delay elements (14). The first chain is the Reference Chain (10), which is driven by a crystal-controlled digital clock input (20). The second chain is the Input Signal Delay Chain (12), which is the delay path for the signal of interest (24). These two chains (10 and 12) are located in physical proximity on the semiconductor die so that variations in manufacturing process, temperature and power supply affect each chain (10 and 12) the same. Each of these delay chains (10 and 12) is comprised of a series of variable delay elements (14) which are digitally controlled by Monitor Logic (18), which measures the delay performance of the Reference Chain (10), and dynamically adjusts the delay of the variable delay elements (14) as induced variations are induced, thereby compensating the delay of the device. Any one of these precise delays can be routed to the output (56) by driving a tap select multiplexer (30) to select the delay of interest. This approach provides precise delays which are constant within a tight tolerance.
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12.发明授权Method for operating a programmable delay circuit and programmable delay circuit 失效一种操作可编程延迟电路和可编程延迟电路的方法。
公开(公告)号：EP0394166B1
公开(公告)日：1994-12-07
申请号：EP90480040.6
申请日：1990-03-13
发明人： Fisher, Jeffrey Herbert , Grasso, Lawrence Joseph , Hoffman, Dale Eugene , Skooglund, Daniel Edward , Young, Diane Kay
IPC分类号： H03K5/135
CPC分类号： H03K5/131 , H03K5/135 , H03K2005/00097 , H03K2005/00104 , H03K2005/00247 , H03K2005/00254
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13.发明公开SELF-COMPENSATING DIGITAL DELAY SEMICONDUCTOR DEVICE WITH SELECTABLE OUTPUT DELAYS AND METHOD THEREFOR 失效具有可选择输出延迟和相关方法DIGITAL自动补偿，半导体延迟电路。
公开(公告)号：EP0626113A1
公开(公告)日：1994-11-30
申请号：EP93904876.0
申请日：1993-02-04
发明人： SORRELLS, Peter , GERINGER, Ned
CPC分类号： H03L7/0805 , H03K5/131 , H03K5/135 , H03K19/00323 , H03K2005/00104 , H03L7/0814
摘要： Dispositif numérique auto-compensé à semiconducteurs de temporisation utilisant deux chaînes identiques (10 et 12) d'éléments de temporisation (14). La première chaîne est la chaîne de référence (10), commandée par une entrée (20) d'horloge numérique pilotée par cristal. La deuxième est la chaîne de temporisation de signal d'entrée (12), qui constitue le cheminement de temporisation du signal en question (24). Ces deux chaînes (10 et 12) sont situées à proximité sur la puce de semiconducteur, de telle sorte que les variations de procédé de production, de température et d'alimentation en énergie influent de manière égale sur l'une et l'autre. Chacune de ces deux chaînes (10 et 12) est incluse dans une série d'éléments (14) de temporisation variable commandés numériquement par une logique de contrôle (18), qui mesure la fonction de temporisation de la chaîne de référence (10) et ajuste dynamiquement la temporisation des éléments de temporisation variable (14) au fur et à mesure que les variations sont induites, compensant ainsi la temporisation du dispositif. L'une quelconque de ces temporisations précises peut être aiguillée vers la sortie (56) en commandant un multiplexeur (30) de sélection de prise pour sélectionner la temporisation désirée. Ce système permet d'obtenir des temporisations précises et constantes selon des tolérances étroites.
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14.发明公开Method for operating a programmable delay circuit and programmable delay circuit 失效运行可编程延迟电路和可编程延迟电路的方法
公开(公告)号：EP0394166A3
公开(公告)日：1991-03-27
申请号：EP90480040.6
申请日：1990-03-13
发明人： Fisher, Jeffrey Herbert , Grasso, Lawrence Joseph , Hoffman, Dale Eugene , Skooglund, Daniel Edward , Young, Diane Kay
IPC分类号： H03K5/135
CPC分类号： H03K5/131 , H03K5/135 , H03K2005/00097 , H03K2005/00104 , H03K2005/00247 , H03K2005/00254
摘要： A method of operating a delay circuit to impose a selected delay on an electronic signal, the delay circuit comprising a plurality of delay stages and means for directing the electronic signal through selected ones of the delay stages, the method comprising the steps of: measuring the actual signal delay through each of the delay stages; and selecting, based on the signal delays obtained in the measuring step, the delay stages through which the electronic signal is directed.
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公开(公告)号：EP0306662A3
公开(公告)日：1989-08-02
申请号：EP88111128.0
申请日：1988-07-12
申请人： TEKTRONIX, INC.
发明人： Greub, Hans J.
IPC分类号： H03K5/13
CPC分类号： H03K3/0231 , H03K5/133 , H03K2005/00052 , H03K2005/00104 , H03K2005/00176 , H03K2005/00182 , H03K2005/00228
摘要： A clock signal is transmitted to nodes (13) of each of several interconnected circuits (16) through a separate adjustable delay circuit (18), the time delay of each delay circuit being adjusted so that the clock signal arrives at each node (13) at the same time, thereby synchronizing operation of the separate integrated circuits one to another. Each delay circuit (18) comprises a set of signal delay elements which can be selectively switched into the clock signal path so that the clock signal delay may be adjusted by adjusting the number of signal delay elements in the clock signal path. Each signal delay element itself has a unit delay adjustable in proportion to an applied control voltage generated by a delay element monitor (30). The delay element monitor (30) measures the unit delay in relation to the period of a stable reference clock and adjusts the delay of each delay element as necessary to ensure that the unit delay remains constant.
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