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公开(公告)号：EP0047382A3
公开(公告)日：1982-10-13
申请号：EP81105735
申请日：1981-07-21
发明人： Goertzel, Gerald
IPC分类号： G06F05/00
CPC分类号： H03M7/42
摘要： This invention relates to a technique for appending prefixed code words to a code word stream conditioned by each least probable symbol in a binary source symbol string. The generation of the prefixed code word from a bounded code word space is managed dynamically by a memory (9) requiring only space availability measures (47, 51) at the start and end of the encoding cycle as input thereto. The memory delivers the prefixed code word of an appropriate derived length to output devices (7) for further processing. The encoder (2), responsive to each input triplet of symbol, symbol estimate, and probability of occurrence measure, generates the space availability measures PC(i) and PC(i-I), and modifies the memory contents so as to reduce the remaining code space. This reduction reflects the fact that the particular code word delivered has been used up and cannot be the prefix of any future delivered code word. The length of each code word requested is composed of two components. The first is the «run» of most probable symbols component, and the second is the terminating least probable symbol component. When the code word length requested exceeds the capacity of the memory to deliver, then the code word length is decreased to the maximum permissible. When the code word space is used up, the memory is considered overflowed and results in a reset in which the code capacity is reinitialized.
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公开(公告)号：EP0030635A3
公开(公告)日：1982-01-13
申请号：EP80107152
申请日：1980-11-18
CPC分类号： B41B19/01 , G06K15/10 , G06K2215/0028 , G09G5/246
摘要： A character compaction and generation method and apparatus which is particularly adapted to the generation of complex characters such as Kanji characters. A dot matrix (Fig. 2-1) defining a given character is compacted into a sparse matrix (Fig. 2-7), with the original character being reconstructed for printing or display from the compacted character defined in the sparse matrix. Each character in the complex character set is compacted and stored in memory (50) one time only, with decompaction being performed each time a given character is to be generated. A set of symbols are defined to represent different patterns which occur frequently in the entire complex character set. Different combinations of the symbols define a given character. The information stored for each sparse matrix representing a given character is comprised of eacn symbol in the sparse matrix, its position, and its size parameter if the symbol represents a family of patterns which differ only in size. Three groups (A, B, C,) of different patterns are defined which occur frequently in the complex character set, namely, a first group (A) which has a fixed size for each pattern, a second group (B) which has one size parameter which must be specified for each pattern, and a third group (Cl which has a plurality of size parameters which must be specified for each pattern. Certain ones of the characters have elements of different patterns which overlap, such that the character may be encoded utilizing less symbols, and according less bytes of data. A given pattern may be generated atthe same time another pattern is being decoded.
摘要翻译： 一种字符压缩和生成方法和装置，其特别适用于生成诸如汉字字符的复杂字符。 定义给定字符的点矩阵被压缩成稀疏矩阵，其中原始字符被重构用于从稀疏矩阵中定义的压缩字符进行打印或显示。 复杂字符集中的每个字符都被压缩并存储在存储器中一次，每当要生成给定字符时执行解压缩。 一组符号被定义为表示在整个复杂字符集中频繁出现的不同模式。 符号的不同组合定义给定的字符。 对于表示给定字符的每个稀疏矩阵存储的信息由稀疏矩阵，其位置和其大小参数中的每个符号组成，如果符号表示仅在大小上不同的模式族。 定义了在组合字符集中频繁出现的三组不同的模式，即对于每个模式具有固定大小的第一组，具有必须为每个模式指定的一个大小参数的第二组，以及第三组 其具有必须为每个模式指定的多个尺寸参数。
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公开(公告)号：EP0141753A3
公开(公告)日：1988-11-02
申请号：EP84402214
申请日：1984-11-05
CPC分类号： G06F5/065 , G06F2205/064 , G06F2205/066
摘要： A data handling system for transferring data between two units, the data being transferred in blocks of a selected number of data words, up to predetermined maximum number. A buffer stores the data being transferred. The buffer includes a plurality of stages (70, 71, 72, 73) arranged serially from an input end (70) to an output end (73), the number of stages being equal in number to the predetermined maximum number of data words that may be transferred in a block. If the number of data words being transferred is less than the predetermined maximum number, as indicated by a control signal (S0, S1) from the unit transmitting the data, the buffer either receives the data in the stage a number of stages from the output end, or transmits the data from the stage a number of stages from the input end, equal to the number of words being transferred in the block.
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公开(公告)号：EP0143005A3
公开(公告)日：1987-04-01
申请号：EP84308148
申请日：1984-11-23
申请人： SONY CORPORATION
CPC分类号： H03M7/14 , G11B20/1426
摘要： A digital signal is divided into a series of base words with m bits of data. Each base word is converted to a converted word having n bits of data, wherein n and m are integers and n is greater than m, and the converted word has a predetermined maximum number of consecutive digital zeroes. The value of every odd-numbered bit of said converted word is detected. The converted word is controlled in response to the result of the detection and modulated as a non-return to zero, inverted-coded digital signal with a DC component of zero.
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15.发明公开Apparatus and method for converting a number in binary format to a decimal format 失效将二进制格式中的数字转换为十进制格式的装置和方法
公开(公告)号：EP0140158A3
公开(公告)日：1986-04-23
申请号：EP84111464
申请日：1984-09-26
CPC分类号： H03M7/08
摘要： A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is described. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. The CPU also includes commercial instruction logic which is used in conjunction with the microprocessor to execute decimal arithmetic operations. The commercial instruction logic also operates under firmware control with the addressing of the firmware microinstructions being controlled by the microprocessor. Also disclosed is the method by which the CPU performs decimal addition, subtraction, multiplication and division arithmetic operations and the method used to convert a number in a binary format to a number in a decimal format and the method used to convert a number in a decimal format to a number in a binary format.
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16.发明公开A recursively operating information handling system and apparatus for recursively decoding an instantaneous FIFO binary arithmetic number string 失效一个可追溯的操作信息处理系统和设备，用于重新解码现存的二进制二进制数字字符串
公开(公告)号：EP0040309A3
公开(公告)日：1982-10-27
申请号：EP81102415
申请日：1981-03-31
IPC分类号： G06F05/00
CPC分类号： H03M7/4006
摘要： An apparatus for ensuring continuous flow through a pipeline processor as it relates to the serial decoding of FIFO Rissanen/Langdon arithmetic string code of binary sources. The pipeline decoder includes a processor (11, 23) and a finite state machine - FSM - (21) in interactive signal relation. The processor generates output binary source signals (18), status signals (31) and K component/K candidate next integer-valued control parameters (LO, k0; L1, k1). These signals and parameters are generated in response to the concurrent application of one bit from successive arithmetic code bits, a K component present integer-value control parameter (52) and K component vector representation (T, TA) of the present internal state (51) of the associated finite state machine. The FSM makes a K-way selection from K candidate next internal states and K candidate next control parameters. This selection uses no more than K 2 + K computations. The selected signals are then applied to the processor in a predetermined displaced time relation to the present signals in the processor. As a consequence, this system takes advantage of the multi-state or "memory" capability of the FSM in order to control the inter-symbol influence and facilitate synchronous multi-stage pipeline decoding.
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公开(公告)号：EP0025323A3
公开(公告)日：1982-01-13
申请号：EP80303017
申请日：1980-08-29
申请人： FUJITSU LIMITED
发明人： Kohich, Ueda , Shigemi, Kamimoto , Akira, Miyata
IPC分类号： G06F05/00
CPC分类号： G06F5/015
摘要： The shift system has rotate parts 12-1 and 12-2 which take divided input data from divided input parts 9-1 and 9-2. Each rotate part 12-1, 12-2 is selectively operable to rotate the divided input data fed thereto and place the rotated data in rotate part outputs 10-1 and 10-2. Select parts 14-1, 14-2 place a selection from the rotated data in rotate part outputs 10-1 and 10-2 in select part output 11, which selection corresponds to the input data shifted by a selected amount. When the rotate parts 12-1, 12-2 rotate data by multiples of 2 A bits only, the selection in select part output 11 corresponds to a shift by a multiple of 2 bits. To effect a shift of the selection in select part output 11 by 0≤Q≤2 A -1 bits, shift parts 16-1 and 16-2 are provided.
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公开(公告)号：EP0149757A3
公开(公告)日：1988-12-14
申请号：EP84114280
申请日：1984-11-27
CPC分类号： G11C7/1006 , G09G1/02
摘要： The system includes a plurality of digital memory units (20, 22,...50) each for storing a plurality of independently addressable binary bits. The units operate together in response to each common bit address to supply a bit from each unit to form an array of bits for a discrete section of a larger array. The units are interconnected through common interconnection buses (e.g. 128, 140) and selective controls (134, 136) to input and output gate connections (e.g. 126, 138) to those buses to provide for selective shifting of bits between units to change the bit array.
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19.发明公开Method and apparatus for generating a noiseless sliding block code for a (1,7) channel with rate 2/3 失效用于产生速率为2/3的（1,7）通道的无噪声滑动块代码的方法和装置
公开(公告)号：EP0070387A3
公开(公告)日：1985-07-03
申请号：EP82105020
申请日：1982-06-08
IPC分类号： G06F05/00
CPC分类号： G06T9/005 , G11B20/1426
摘要： An encoder for producing a run length limited code useful in magnetic recording channels producing sequences which have a minimum of 1 zero and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that maps 2 bits of unconstrained data (s) into 3 bits of constrained date (y). The encoder comprises a fairly simple logic network (20) and is a finite state machine whose internal state description requires 3 bits (x). It possesses the attractive feature of certain reset data blocks which reset it to a fixed state. The error propagation due to a random error is 5 bits. The hardware implementation is extremely simple and can operate at very high data speeds.
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公开(公告)号：EP0083420A3
公开(公告)日：1984-08-22
申请号：EP82111125
申请日：1982-12-02
发明人： Chang, Ifay Fay
IPC分类号： G06F05/00
CPC分类号： G06F17/2205 , G06F17/2217 , Y10S707/99936
摘要： Words input to an information processing system (24) ,character-by-character are given unique unitary representations independent of alphanumeric content and order. A user selects a particular vocabulary set containing the unique unitary representations of each word in the vocabulary set. When a word is input into the system, it is matched with its unique unitary representation. This representation is provided to storage (22) and output devices (36) in the system. It is also utilized in text transmission (23). Words not found in the preselected vocabulary set are encoded character-by-character. Vocabulary sets may be chosen so as to minimize the occurrence of this last event.
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