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21.发明公开VIDEO DECODER APPARATUS USING NON-REFERENCE FRAME AS AN ADDITIONAL PREDICTION SOURCE AND METHOD THEREFOR 失效BILDDEKODIERGERÄT和方法使用非参考图像作为附加源预测
公开(公告)号：EP0821857A1
公开(公告)日：1998-02-04
申请号：EP96912840.0
申请日：1996-04-17
CPC分类号： H04N19/577
摘要： A video decoder system, such as for use with MPEG video compression, uses a previous B-frame as an additional prediction source for the current B-frame, along with the past and future reference frames as defined by the MPEG specification. In one embodiment, a given macroblock within a current B-frame 'N' reuses pixel values from the previous B-frame 'N-1' if they are 'similar enough' to the anticipated pixels which would otherwise need to be computed. For a given macroblock, motion vectors for both B-frames are compared: if they differ by less than a similarity threshold value, then the pixel values from the previous B-frame are reused without further computation. The similarity threshold may be adaptively adjusted to reduce the computational burden of video decompression, while affording a gradual degradation of picture quality, rather than wholesale skipping of entire frames.
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22.发明授权A COMPUTER SYSTEM INCLUDING A SECURE EXECUTION MODE - CAPABLE CPU AND A SECURITY SERVICES PROCESSOR CONNECTED VIA A SECURE COMMUNICATION PATH 有权适当的CPU以及安全处理器通过安全通信的方式与安全模式对应的计算机系统被链接
公开(公告)号：EP1495394B1
公开(公告)日：2008-07-23
申请号：EP03724195.7
申请日：2003-04-18
发明人： MCGRATH, Kevin, J. , STRONGIN, Geoffrey, S. , GULICK, Dale, E. , HUGHES, William A. , CHRISTIE, David, S.
IPC分类号： G06F21/02
CPC分类号： G06F9/4403 , G06F21/10 , G06F21/74
摘要： A computer system (10, 20) includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes an input/output (I/O) interface (120, 220) coupled to the processor via an I/O link (225). The I/O interface may receive transactions performed as a result of the execution of the security initialization instruction. The transactions include at least a portion of the secure operating system code segment. The I/O interface may also determine whether the processor is a source of the transactions. The computer system further includes a security services processor (130) coupled to the I/O interface via a peripheral bus (135). The I/O interface may convey the transactions to the security services processor dependent upon determining that the processor is the source of the transactions.
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公开(公告)号：EP1407628B1
公开(公告)日：2006-04-05
申请号：EP02742079.3
申请日：2002-06-12
发明人： SMITH, David, W. , BARNES, Brian, C. , COLE, Terry, L. , SCHMIDT, Rodney , STRONGIN, Geoffrey, S. , BARCLAY, Michael
摘要： A communications system (10) includes a physical layer hardware unit (220) and a processing unit (110). The physical layer hardware unit (220) is adapted to communicate data over a communications channel (40) in accordance with assigned transmission parameters. The physical layer hardware unit (220) is adapted to receive an incoming signal over the communications channel (40) and sample the incoming signal to generate a digital received signal. The processing unit (110) is adapted to execute a standard mode driver (240) in a standard mode of operation and a privileged mode driver (250) in a privileged mode of operation. The standard mode driver (240) includes program instructions adapted to extract control codes (280) from the digital received signal and configure the physical layer hardware unit (220) assigned transmission parameters based on the control codes (280). The privileged mode driver (250) includes prograni instructions adapted to independently extract secure control codes (310) from the digital received signal, determine an operational characteristic of the physical layer hardware unit (220), and signal a security violation in response to the operational characteristic being inconsistent with the secure control codes (310).
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24.发明授权SOFTWARE MODEM WITH PRIVILEGED MODE DECRYPTION OF CONTROL CODES 有权与BEVORRECHTIGTEM操作软件调制解调器控制参数DECODE
公开(公告)号：EP1405491B1
公开(公告)日：2006-03-01
申请号：EP02752048.5
申请日：2002-06-12
发明人： SMITH, David, W. , BARNES, Brian, C. , COLE, Terry, L. , SCHMIDT, Rodney , STRONGIN, Geoffrey, S. , BARCLAY, Michael
摘要： A communications system (10) includes a physical layer hardware unit (220) and a processing unit (110). The physical layer hardware unit (220) is adapted to communicate data over a communications channel (40) in accordance with assigned transmission parameters. The physical layer hardware unit (220) is adapted to receive an incoming signal over the communications channel (40) and sample the incoming signal to generate a digital received signal. The processing unit (110) is adapted to execute a standard mode driver (240) in a standard mode of operation and a privileged mode driver (250) in a privileged mode of operation. The standard mode driver (240) includes program instructions adapted to extract encrypted data (260) from the digital received signal and pass the encrypted data (260) to the privileged mode driver (250). The privileged mode driver (250) includes program instructions adapted to decrypt the encrypted data (260) to generate decrypted data (270) including control codes (280) and transfer the control codes (280) to the physical layer hardware unit (220). The physical layer hardware unit (220) is adapted to configure its assigned transmission parameters based on the control codes (280). A method for configuring a transceiver (50) includes receiving encrypted data (260) over a communications channel in a standard processing mode of a processing unit (110); transitioning the processing unit (110) into a privileged processing mode; decrypting the encrypted data (260) in the privileged processing mode; extracting control codes (280) from the decrypted data (270) in the privileged processing mode; and transmitting an upstream signal over the communications channel (40) based on transmission assignments defined by the control codes (280).
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25.发明公开INITIALIZATION OF A COMPUTER SYSTEM INCLUDING A SECURE EXECUTION MODE-CAPABLE PROCESSOR 有权初始化一个for安全模式适当的处理器的计算机系统
公开(公告)号：EP1495401A2
公开(公告)日：2005-01-12
申请号：EP03718435.5
申请日：2003-04-18
发明人： MCGRATH, Kevin, J. , STRONGIN, Geoffrey, S. , CHRISTIE, David, S. , HUGHES, William, A. , GULICK, Dale, E.
IPC分类号： G06F9/445
CPC分类号： G06F9/4403 , G06F12/1441 , G06F12/1458 , G06F12/1491
摘要： The initialization of a computer system (10) including a secure execution mode-capable processor (100) includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory (110). The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.
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26.发明公开METHOD AND APPARATUS FOR MULTI-TABLE ACCESSING OF INPUT/OUTPUT DEVICES USING TARGET SECURITY 审中-公开方法和设备访问输入/输出设备的多个表使用目标安全
公开(公告)号：EP1468363A2
公开(公告)日：2004-10-20
申请号：EP02759662.6
申请日：2002-09-12
IPC分类号： G06F12/14
CPC分类号： G06F12/1491
摘要： A method and an apparatus for performing an I/O device access using targeted security. A software object (350) is executed. A security level for the software object (350) is established. A multi-table input/output (I/O) space access is performed using at least one of the security levels. The function of the software object (350) is executed.
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公开(公告)号：EP1410143A2
公开(公告)日：2004-04-21
申请号：EP02719514.8
申请日：2002-04-17
IPC分类号： G06F1/00
CPC分类号： G06F9/24
摘要： Methods, devices, and systems for closing back door access mechanisms. A processor includes a first register configured to store one or more hardware-debug-test (HDT) enable bits, a first control logic coupled to receive a plurality of HDT input signals, and a second control logic coupled to the first register. The first control logic is coupled to access the first register. The second control logic is configured to store one or more default values in the first register in response to a reset of the processor. Another processor includes a first control logic coupled to receive a plurality of microcode inputs, a first register coupled to the first control logic, and a second control logic coupled to the first register. The first register is configured to store one or more microcode loader enable bits. The second control logic is configured to store one or more default values in the first register in response to a reset of the processor.
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公开(公告)号：EP1407627A1
公开(公告)日：2004-04-14
申请号：EP02742072.8
申请日：2002-06-12
发明人： BARNES, Brian, C. , SMITH, David, W. , COLE, Terry, L. , SCHMIDT, Rodney , STRONGIN, Geoffrey, S. , BARCLAY, Michael
CPC分类号： H04L63/0428 , G06F21/55 , H04L63/08
摘要： A communication system (10) includes a physical layer hardware unit (220) and a processing unit (100). The physical layer hardware unit (220) is adapted to communicate data over a communications channel (40) in accordance with assigned transmission parameters. The physical layer hardware unit (220) is adapted to receive an incoming signal over the communications channel (40) and sample the incoming signal to generate a digital received signal. The processing unit (100) is adapted to execute a software driver (240) including program instructions adapted to extract control codes from the digital received signal, generate an authentication code, and transfer the control codes and the authentication code to the physical layer hardware unit (220). The physical layer hardware unit (220) is adapted to signal a security violation in response to the control codes being inconsistent with the authentication code.
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公开(公告)号：EP1374064A2
公开(公告)日：2004-01-02
申请号：EP02704314.0
申请日：2002-02-01
IPC分类号： G06F12/14
CPC分类号： G06F21/79 , G06F12/1483
摘要： The present invention provides a method and apparatus for securing portions of a memory. The method includes identifying information for protection and indicating at least one physical address of a memory that houses the information as at least one of read and write disabled. The method includes receiving a request from a program to access the information. The method further includes accessing the information in response to determining that the program has the authority to access the information.
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30.发明授权VIDEO DECODER APPARATUS USING NON-REFERENCE FRAME AS AN ADDITIONAL PREDICTION SOURCE AND METHOD THEREFOR 失效BILDDEKODIERGERÄT和方法使用非参考图像作为附加源预测
公开(公告)号：EP0821857B1
公开(公告)日：1999-09-01
申请号：EP96912840.4
申请日：1996-04-17
IPC分类号： H04N7/46
CPC分类号： H04N19/577
摘要： A video decoder system, such as for use with MPEG video compression, uses a previous B-frame as an additional prediction source for the current B-frame, along with the past and future reference frames as defined by the MPEG specification. In one embodiment, a given macroblock within a current B-frame "N" reuses pixel values from the previous B-frame "N-1" if they are "similar enough" to the anticipated pixels which would otherwise need to be computed. For a given macroblock, motion vectors for both B-frames are compared: if they differ by less than a similarity threshold value, then the pixel values from the previous B-frame are reused without further computation. The similarity threshold may be adaptively adjusted to reduce the computational burden of video decompression, while affording a gradual degradation of picture quality, rather than wholesale skipping of entire frames.
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