公开(公告)号：EP1442389A2

公开(公告)日：2004-08-04

申请号：EP02780299.0

申请日：2002-09-12

申请人： Advanced Micro Devices, Inc.

发明人： GULICK, Dale, E.

IPC分类号： G06F15/78

CPC分类号： H04L41/00 ,  G06F13/387

摘要： An integrated circuit, a computer system, and a method of operating the computer system. The integrated circuit includes an internal bus and a microcontroller connected to the internal bus. The microcontroller is configured to master the internal bus. An Ethernet controller may also be coupled to the internal bus with a plurality of buffers coupled between the microcontroller and the Ethernet controller for buffering data between the microcontroller and the Ethernet controller. The Ethernet controller and the microcontroller are then configured to exchange data over the internal bus.

摘要翻译： 集成电路，计算机系统和操作计算机系统的方法。 集成电路包括内部总线，连接到内部总线的微控制器，耦合到内部总线的以太网控制器以及耦合在微控制器和以太网控制器之间的多个缓冲器，用于缓冲微控制器和以太网控制器之间的数据。 微控制器配置为掌握内部总线。 以太网控制器和微控制器配置为通过内部总线交换数据。

公开(公告)号：EP1428095A2

公开(公告)日：2004-06-16

申请号：EP02723866.6

申请日：2002-04-17

申请人： ADVANCED MICRO DEVICES INC.

发明人： WEBER, Frederick, D. ,  GULICK, Dale, E. ,  STRONGIN, Geoffrey, S.

IPC分类号： G06F1/00

CPC分类号： G06F21/74 ,  G06F21/53 ,  G06F21/575 ,  G06F21/72 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2107 ,  G06F2221/2141 ,  G06F2221/2147

摘要： A method and system for providing an external locking mechanism for memory locations. The memory includes a first plurality of storage locations configured with BIOS data and a second plurality of storage locations. The second plurality of storage locations includes a first plurality of blocks readable only in SMM and a second plurality of blocks readable in SMM and at least one operating mode other than SMM. The computer system includes a bus, a memory coupled to the bus, and a device coupled to access the memory over the bus. The memory includes a plurality of storage locations, divided into a plurality of memory units. The device includes one or more locks configured to control access to one or more of the plurality of memory units.

摘要翻译： 一种用于为存储器位置提​​供外部锁定机构的方法和系统。 存储器包括配置有BIOS数据的第一多个存储位置和第二多个存储位置。 第二多个存储位置包括仅在SMM中可读的第一多个块和在SMM中可读的第二多个块以及除SMM之外的至少一个操作模式。 计算机系统包括总线，耦合到总线的存储器，以及耦合到通过总线访问存储器的设备。 存储器包括分成多个存储单元的多个存储位置。 该设备包括配置成控制对多个存储器单元中的一个或多个的访问的一个或多个锁。

公开(公告)号：EP1495394B1

公开(公告)日：2008-07-23

申请号：EP03724195.7

申请日：2003-04-18

申请人： ADVANCED MICRO DEVICES, INC.

发明人： MCGRATH, Kevin, J. ,  STRONGIN, Geoffrey, S. ,  GULICK, Dale, E. ,  HUGHES, William A. ,  CHRISTIE, David, S.

IPC分类号： G06F21/02

CPC分类号： G06F9/4403 ,  G06F21/10 ,  G06F21/74

摘要： A computer system (10, 20) includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes an input/output (I/O) interface (120, 220) coupled to the processor via an I/O link (225). The I/O interface may receive transactions performed as a result of the execution of the security initialization instruction. The transactions include at least a portion of the secure operating system code segment. The I/O interface may also determine whether the processor is a source of the transactions. The computer system further includes a security services processor (130) coupled to the I/O interface via a peripheral bus (135). The I/O interface may convey the transactions to the security services processor dependent upon determining that the processor is the source of the transactions.

公开(公告)号：EP1495401A2

公开(公告)日：2005-01-12

申请号：EP03718435.5

申请日：2003-04-18

申请人： ADVANCED MICRO DEVICES INC.

发明人： MCGRATH, Kevin, J. ,  STRONGIN, Geoffrey, S. ,  CHRISTIE, David, S. ,  HUGHES, William, A. ,  GULICK, Dale, E.

IPC分类号： G06F9/445

CPC分类号： G06F9/4403 ,  G06F12/1441 ,  G06F12/1458 ,  G06F12/1491

摘要： The initialization of a computer system (10) including a secure execution mode-capable processor (100) includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory (110). The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.

公开(公告)号：EP1449100A1

公开(公告)日：2004-08-25

申请号：EP02773344.3

申请日：2002-09-12

申请人： ADVANCED MICRO DEVICES INC.

发明人： GULICK, Dale, E.

IPC分类号： G06F13/40

CPC分类号： G06F13/4022 ,  G06F2213/0024 ,  G06F2213/0026

摘要： A switching I/O node for connection in a multiprocessor computer system. An input/output node switch (400) includes a bridge unit (450) and a packet bus switch unit (430) implemented on an integrated circuit chip. The bridge unit may receive a plurality of peripheral transactions from a peripheral bus (455) and may transmit a plurality of upstream packet transactions corresponding to the plurality of peripheral transactions. The packet bus switch may receive the upstream packet transactions on an internal point-to-point packet bus link (435) and may determine a destination of each of the upstream packet transactions. The packet bus switch may further route selected ones of the upstream packet transactions to a first processor interface coupled to a first point-to-point packet bus link (401) and route others of the upstream packet transactions to a second processor interface coupled to a second point-to-point packet bus link (402) in response to determining the destination each of the upstream packet transactions.

公开(公告)号：EP0961978B1

公开(公告)日：2003-08-27

申请号：EP98908574.1

申请日：1998-02-14

申请人： Advanced Micro Devices, Inc.

发明人： GULICK, Dale, E.

IPC分类号： G06F13/42

CPC分类号： G06F13/423

摘要： A bus connects a first and second integrated circuit. The bus includes a frame sync line which indicates the beginning of a frame when asserted, each frame containing a predetermined number time slots. A data out line provides data from the first to the second integrated circuit. The data represents the state of signals to be provided on output terminals of the second integrated circuit. Each of the data bits is assigned one of the time slots in the frame. A data in line provides a predetermined number of second data bits from the second to the first integrated circuit during each frame. Each of the second data bits is assigned one of the time slots and includes data including data bits indicating the state of input terminals of the second integrated circuit. A clock signal defines the time slots within the frame. The bus operates to provide frames substantially continuously between the first and second integrated circuit while the first and second integrated circuits.

摘要翻译： 总线连接第一和第二集成电路。 总线包括一个帧同步线，该帧同步线指示帧被确立时的开始，每个帧包含预定数量的时隙。 数据输出线提供来自第一至第二集成电路的数据。 数据表示要在第二集成电路的输出端子上提供的信号的状态。 每个数据比特被分配给帧中的一个时隙。 行内数据在每帧期间提供从第二集成电路到第一集成电路的预定数量的第二数据位。 每个第二数据比特被分配一个时隙并且包括包含指示第二集成电路的输入端的状态的数据比特的数据。 时钟信号定义了帧内的时隙。 总线用于在第一和第二集成电路之间基本连续地提供帧，同时第一和第二集成电路。

公开(公告)号：EP1000398B1

公开(公告)日：2002-11-13

申请号：EP98928943.4

申请日：1998-06-10

申请人： ADVANCED MICRO DEVICES INC.

发明人： GULICK, Dale, E.

IPC分类号： G06F13/12

CPC分类号： G06F13/122

摘要： A computer system includes a central processing unit directly couled to a peripheral device. The peripheral device transmits and receives data from and to the central processing unit. An MMx unit within the CPU includes data buffers for storing data. Data from the multimedia device is stored in a receive buffer and subsequently retrieved by the MMx unit for processing. Data from the MMx unit is stored in a transmit buffer and subsequently retrieved by the multimedia device. The receive buffer may include a concatenator for combining data words received from the multimedia device into a multimedia data word. The transmit buffer may include a de-concatenator for dividing a multimedia data word into a plurality of data words for transmission to the multimedia device. The data buffers provide signals indicating the relative level of fullness or emptiness of the buffers. The signals are used to adjust the rate at which data is processed. In one embodiment, data is transferred to the multimedia device in a serial fashion. In this embodiment, a serial-to-parallel converter is coupled between the multimedia device in the receive buffer and a parallel-to-serial converter is coupled between the transmit buffer and the multimedia device.

公开(公告)号：EP0961976A1

公开(公告)日：1999-12-08

申请号：EP98906381.0

申请日：1998-02-14

申请人： Advanced Micro Devices, Inc.

发明人： GULICK, Dale, E.

IPC分类号： G06F13

CPC分类号： G06F13/4027 ,  G06F13/385 ,  G06F13/405 ,  Y02D10/14 ,  Y02D10/151

摘要： A first integrated circuit includes interface logic between legacy devices and an expansion bus. A second integrated circuit provides input and output terminals for the interface logic. A bus couples the first and second integrated circuits and transfers data substantially continuously between the first and second integrated circuits. The data includes output signals from the interface logic which is provided to the output terminals of the second integrated circuit and input signals for the interface logic from the input terminals of the second integrated circuit. The data is transferred between the first and second integrated circuits in frames which includes a predetermined number of data bits and preassigned slots for the states of the input and output signals, so as to continuously transfer the state of the input and output signals to and from the input and output pins of the second integrated circuit at a predetermined rate. The second integrated circuit includes input/output terminals to couple to legacy devices such as a keyboard, a mouse, a game port, a musical instrument digital interface (MIDI) port, a floppy drive, a PC speaker and an infrared port.

公开(公告)号：EP1483674B1

公开(公告)日：2006-04-05

申请号：EP03711337.0

申请日：2003-02-28

申请人： ADVANCED MICRO DEVICES, INC.

发明人： HESSE, Siegfried, Kay ,  GULICK, Dale, E.

IPC分类号： G06F13/38

CPC分类号： G06F13/387

摘要： A USB host controller is provided for handling the data traffic between at least one USB device and a system memory of a computer system. The USB host controller comprises a data fetch unit (530) for fetching data elements from the system memory, a storage unit (535) for storing the fetched data elements, and a transaction processing unit (570) for processing transactions sent to or received from the USB device dependent on the fetched data elements stored in the storage unit. The data fetch unit and the transaction processing unit are arranged for operating asynchronously. The host controller may be USB 2.0 compliant and may be realized in a southbridge.

公开(公告)号：EP1449100B1

公开(公告)日：2006-03-29

申请号：EP02773344.3

申请日：2002-09-12

申请人： ADVANCED MICRO DEVICES, INC.

发明人： GULICK, Dale, E.

IPC分类号： G06F13/40

CPC分类号： G06F13/4022 ,  G06F2213/0024 ,  G06F2213/0026

摘要： A switching I/O node for connection in a multiprocessor computer system. An input/output node switch (400) includes a bridge unit (450) and a packet bus switch unit (430) implemented on an integrated circuit chip. The bridge unit may receive a plurality of peripheral transactions from a peripheral bus (455) and may transmit a plurality of upstream packet transactions corresponding to the plurality of peripheral transactions. The packet bus switch may receive the upstream packet transactions on an internal point-to-point packet bus link (435) and may determine a destination of each of the upstream packet transactions. The packet bus switch may further route selected ones of the upstream packet transactions to a first processor interface coupled to a first point-to-point packet bus link (401) and route others of the upstream packet transactions to a second processor interface coupled to a second point-to-point packet bus link (402) in response to determining the destination each of the upstream packet transactions.