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公开(公告)号：EP0859980B1
公开(公告)日：1999-12-29
申请号：EP96924628.9
申请日：1996-07-19
摘要： A microcode patching method and apparatus provide for fetching of microcode from an external source which, under appropriate conditions, replaces direct reading of microcode from a microcode ROM. In a decoder having a capability to concurrently dispatch up to four instructions and each dispatch pathway having two alternative decoding pathways including a fastpath pathway and a microcode ROM pathway, a technique and apparatus for patching the microcode ROM is described. This technique and apparatus provide that execution codes from the microcode ROM are selectively replaced, during decoding, by codes taken from an external source, such as from an external memory via a byte queue.
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2.发明公开A MULTI-THREADED MICROPROCESSOR CONFIGURED TO EXECUTE INTERRUPT SERVICE ROUTINES AS A THREAD 失效多线程微处理器设计用于执行中断处理例程中的使用线程
公开(公告)号：EP0898743A1
公开(公告)日：1999-03-03
申请号：EP97924753.0
申请日：1997-05-16
IPC分类号： G06F9
CPC分类号： G06F9/4812 , G06F9/3851 , G06F9/3885 , G06F9/462
摘要： A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is capable of executing at least two threads concurrently: a task and an interrupt service routine. Interrupt service routines may be executed without disturbing a task's context and without performing a context save operation. Instead, the interrupt service routine accesses a context which is independent of the context of the task. In another embodiment, the context file includes multiple interrupt service routine contexts. Multiple ISR context storages allow for nested interrupts to be performed concurrently. In yet another embodiment, the microprocessor is configured to execute multiple tasks and multiple interrupt service routines concurrently. Multiple tasks may be executed concurrently by the microprocessor in addition to executing multiple interrupt service routines concurrently. In still another embodiment, the microprocessor includes a primary context and multiple local context storages coupled to each of its execution units. A given execution unit may execute instructions referencing the primary context or the local context connected thereto.
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3.发明授权A COMPUTER SYSTEM INCLUDING A SECURE EXECUTION MODE - CAPABLE CPU AND A SECURITY SERVICES PROCESSOR CONNECTED VIA A SECURE COMMUNICATION PATH 有权适当的CPU以及安全处理器通过安全通信的方式与安全模式对应的计算机系统被链接
公开(公告)号：EP1495394B1
公开(公告)日：2008-07-23
申请号：EP03724195.7
申请日：2003-04-18
发明人： MCGRATH, Kevin, J. , STRONGIN, Geoffrey, S. , GULICK, Dale, E. , HUGHES, William A. , CHRISTIE, David, S.
IPC分类号： G06F21/02
CPC分类号： G06F9/4403 , G06F21/10 , G06F21/74
摘要： A computer system (10, 20) includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes an input/output (I/O) interface (120, 220) coupled to the processor via an I/O link (225). The I/O interface may receive transactions performed as a result of the execution of the security initialization instruction. The transactions include at least a portion of the secure operating system code segment. The I/O interface may also determine whether the processor is a source of the transactions. The computer system further includes a security services processor (130) coupled to the I/O interface via a peripheral bus (135). The I/O interface may convey the transactions to the security services processor dependent upon determining that the processor is the source of the transactions.
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4.发明公开INITIALIZATION OF A COMPUTER SYSTEM INCLUDING A SECURE EXECUTION MODE-CAPABLE PROCESSOR 有权初始化一个for安全模式适当的处理器的计算机系统
公开(公告)号：EP1495401A2
公开(公告)日：2005-01-12
申请号：EP03718435.5
申请日：2003-04-18
发明人： MCGRATH, Kevin, J. , STRONGIN, Geoffrey, S. , CHRISTIE, David, S. , HUGHES, William, A. , GULICK, Dale, E.
IPC分类号： G06F9/445
CPC分类号： G06F9/4403 , G06F12/1441 , G06F12/1458 , G06F12/1491
摘要： The initialization of a computer system (10) including a secure execution mode-capable processor (100) includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory (110). The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.
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5.发明授权CPU ACCESSING AN EXTENDED REGISTER SET IN AN EXTENDED REGISTER MODE AND CORRESPONDING METHOD 有权CPU上的延伸设置高级模式寄存器中的寄存器访问及相应方法
公开(公告)号：EP1320800B1
公开(公告)日：2004-05-19
申请号：EP01961938.6
申请日：2001-08-07
发明人： CHRISTIE, David, S.
CPC分类号： G06F9/30138 , G06F9/30036 , G06F9/30076 , G06F9/30112 , G06F9/30185 , G06F9/30189
摘要： A central processing unit (CPU) (32) is described including a register file (60) and an execution core (52) coupled to the register file (60). The register file (60) includes a standard register set (84) and an extended register set (86). The standart register set (84) includes multiple standard registers, and the extended register set (86) includes multiple extended registers. The execution core (52) fetches and executes instructions, and receives a signal indicating an operating mode of the CPU (32). The execution core (52) responds to an instruction (80) by accessing at least one extended register if the signal indicates the CPU (32) is operating in an extended register mode and the instruction (80) includes a prefix portion (82) including information used to access the at least one extended register.
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6.发明授权PREVENTING UNINTENDED LOSS OF TRANSACTIONAL DATA IN HARDWARE TRANSACTIONAL MEMORY SYSTEMS 有权预防硬件事务存储系统中事务数据意外的损失
公开(公告)号：EP2641171B1
公开(公告)日：2018-01-03
申请号：EP11785547.8
申请日：2011-11-09
发明人： CHUNG, Jaewoong , CHRISTIE, David, S. , HOHMUTH, Michael, P. , DIESTELHORST, Stephan , POHLACK, Martin, T. , YEN, Luke
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3857
摘要： A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.
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7.发明授权A MULTI-THREADED MICROPROCESSOR CONFIGURED TO EXECUTE INTERRUPT SERVICE ROUTINES AS A THREAD 失效多线程微处理器设计用于执行中断处理例程中的AS THREADS
公开(公告)号：EP0898743B1
公开(公告)日：2000-01-12
申请号：EP97924753.3
申请日：1997-05-16
IPC分类号： G06F9/46
CPC分类号： G06F9/4812 , G06F9/3851 , G06F9/3885 , G06F9/462
摘要： A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is capable of executing at least two threads concurrently: a task and an interrupt service routine. Interrupt service routines may be executed without disturbing a task's context and without performing a context save operation. Instead, the interrupt service routine accesses a context which is independent of the context of the task. In another embodiment, the context file includes multiple interrupt service routine contexts. Multiple ISR context storages allow for nested interrupts to be performed concurrently. In yet another embodiment, the microprocessor is configured to execute multiple tasks and multiple interrupt service routines concurrently. Multiple tasks may be executed concurrently by the microprocessor in addition to executing multiple interrupt service routines concurrently. In still another embodiment, the microprocessor includes a primary context and multiple local context storages coupled to each of its execution units. A given execution unit may execute instructions referencing the primary context or the local context connected thereto.
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8.发明授权MICROPROCESSOR USING INSTRUCTION FIELD TO SPECIFY EXPANDED FUNCTIONALITY AND CORRESPONDING METHOD 失效如果指定由命令字段和程序，以先进的功能微处理器
公开(公告)号：EP0834118B1
公开(公告)日：1999-03-31
申请号：EP96923277.6
申请日：1996-06-07
IPC分类号： G06F9/318
CPC分类号： G06F9/3013 , G06F9/30101 , G06F9/30185 , G06F9/34 , G06F9/3844
摘要： A microprocessor is provided which expands the functionality and/or performance of the implemented architecture in transparent and/or non-transparent ways. The microprocessor is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode and to use the prefix value to control internal and/or external functions. Additionally, the microprocessor may be configured to signal a change or modification of the normal execution of the instruction(s) which follow. Many embodiments are shown which use the segment override prefixes to expand the performance or capability of the microprocessor. Backward compatibility with older implementations of the x86 architecture may be maintained when implementing transparent embodiments.
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公开(公告)号：EP2332043A1
公开(公告)日：2011-06-15
申请号：EP09789014.9
申请日：2009-07-28
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/30185 , G06F9/30189 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3863 , G06F9/468 , G06F9/52
摘要： A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition.
摘要翻译： 公开了一种系统和方法，其中耦合到共享存储器的多个处理器的处理器被配置为根据处理器的第一事务模式启动执行代码段。 所述处理器被配置为对所述代码段内的所述共享存储器执行对所述多个处理器的单个原子事务的多个受保护存储器访问操作。 处理器还被配置为在代码段内启动根据处理器的第二事务模式执行代码段的子部分，其中第一和第二事务模式各自与相应的恢复动作相关联，处理器 被配置为响应于检测到中止条件而执行。
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10.发明公开
公开(公告)号：EP1509839A2
公开(公告)日：2005-03-02
申请号：EP02795889.1
申请日：2002-12-17
摘要： A method and system (400A-B) for performing the method is provided. The method includes executing an insecure routine and receiving a request from the insecure routine. The method also includes performing a first evaluation of the request in hardware, and performing a second evaluation of the request in a secure routine in software. The computer system (400A-B) includes a processor (404) configurable to execute a secure routine and an insecure routine. The computer system (400A-B) also includes hardware coupled to perform a first evaluation of a request associated with the insecure routine. The hardware is further configured to provide a notification of the request to the secure routine. The secure routine is configured to perform a second evaluation of the request. The secure routine is further configured to deny a requested response to the request.
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