摘要:
A CMIS circuit device such as an IC chip of a semiconductor memory device which is made selectable by using at least two chip-select signals (CS,, CS 2 ) having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state and a chip-unselected state upon receiving the above-mentioned chip-select signals. The chip-select control circuit comprises a CMIS inverter means (IV,) for inverting one of the chip-select signals (CS 2 ) and a CMIS logic gate means (lV 2 ) for receiving an output signal (a) of the CMIS) inverter means and the other chip select signal or signals (CS 1 ) and for outputting an internal chip-select control signal (CS). The CMIS inverter means (IV 1 ) comprises a CMIS inverter (Q 20 , Q 21 ) and one or more control transistors (Q 19 ) which receive the other chip-select signal or signals (CS 1 ) at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.
摘要:
In a static semiconductor memory device incorporating redundancy memory cells (C RO , CR1, ...), a connecting/disconnecting circuit is linked between a power supply terminal (Vcc) and one of the bit lines (Bo, B o, ...), thereby reducing or cutting off a current flowing through a defective memory cell.
摘要:
A semiconductor memory device comprising bit lines, word lines, memory cells arranged at the intersections of the bit lines and the word lines, data buses, and transfer gate transistors connected between the bit lines and the data buses, an information signal being read out to the data buses from the memory cells through the bit lines by turning on the transfer gate transistors and the transfer gate transistors having a threshold voltage smaller than that of the transistors used in the other circuits of the semiconductor memory device.
摘要:
A CMIS circuit device such as an IC chip of a semiconductor memory device which is made selectable by using at least two chip-select signals (CS,, CS 2 ) having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state and a chip-unselected state upon receiving the above-mentioned chip-select signals. The chip-select control circuit comprises a CMIS inverter means (IV,) for inverting one of the chip-select signals (CS 2 ) and a CMIS logic gate means (lV 2 ) for receiving an output signal (a) of the CMIS) inverter means and the other chip select signal or signals (CS 1 ) and for outputting an internal chip-select control signal (CS). The CMIS inverter means (IV 1 ) comprises a CMIS inverter (Q 20 , Q 21 ) and one or more control transistors (Q 19 ) which receive the other chip-select signal or signals (CS 1 ) at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.
摘要:
A semiconductor memory device such as a static-type random-access memory device comprising an address-change detection circuit which generates a pulse signal when an input address signal has changed and a latch circuit which temporarily stores the readout signal from a selected memory cell. The readout signal is input into the latch circuit in synchronization with the timing of the pulse signal or a short time after the pulse signal, and the readout data from the semiconductor memory device is obtained from the latch circuit, thereby increasing the time interval during which the readout data from the semiconductor memory device is available.
摘要:
n a buffer circuit comprising a first, a second and a third transistor (31, 32, 33) and a capacitor (4) for bootstrap action, an inverter (52) is connected to the output point (6) at which the second and third transistors are connected in series, the inverter inverting the output signal (Sout) and supplying the inverted signal (S52) to the gate of the first transistor (31), thereby to increase the rate of rise of the leading edge of an output signal pulse.
摘要:
A semiconductor resistor element comprising a semiconductor film (14) which has a desired shape and electrode wirings (20a-20b) at both ends thereof, and a control electrode (18) provided between the two ends of the semiconductor film (14) via an insulating film (16). The control electrode (18) is served with a control voltage which controls the resistance of the semiconductor film. Namely, the control electrode is served with a control voltage that changes with the change in temperature to offset the change in resistance of the semiconductor film caused by the change in temperature.