CMIS circuit device
    21.
    发明公开
    CMIS circuit device 失效
    CMIS电路设备

    公开(公告)号:EP0107355A3

    公开(公告)日:1986-12-17

    申请号:EP83305677

    申请日:1983-09-23

    申请人: FUJITSU LIMITED

    IPC分类号: G11C08/00

    摘要: A CMIS circuit device such as an IC chip of a semiconductor memory device which is made selectable by using at least two chip-select signals (CS,, CS 2 ) having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state and a chip-unselected state upon receiving the above-mentioned chip-select signals. The chip-select control circuit comprises a CMIS inverter means (IV,) for inverting one of the chip-select signals (CS 2 ) and a CMIS logic gate means (lV 2 ) for receiving an output signal (a) of the CMIS) inverter means and the other chip select signal or signals (CS 1 ) and for outputting an internal chip-select control signal (CS). The CMIS inverter means (IV 1 ) comprises a CMIS inverter (Q 20 , Q 21 ) and one or more control transistors (Q 19 ) which receive the other chip-select signal or signals (CS 1 ) at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.

    Semiconductor memory device
    25.
    发明公开

    公开(公告)号:EP0090591A3

    公开(公告)日:1984-08-15

    申请号:EP83301617

    申请日:1983-03-23

    申请人: FUJITSU LIMITED

    IPC分类号: G11C11/00 G11C05/00 G11C07/00

    CPC分类号: G11C7/1006 G11C11/419

    摘要: A semiconductor memory device comprising bit lines, word lines, memory cells arranged at the intersections of the bit lines and the word lines, data buses, and transfer gate transistors connected between the bit lines and the data buses, an information signal being read out to the data buses from the memory cells through the bit lines by turning on the transfer gate transistors and the transfer gate transistors having a threshold voltage smaller than that of the transistors used in the other circuits of the semiconductor memory device.

    CMIS circuit device
    26.
    发明公开
    CMIS circuit device 失效
    CMIS-Schaltungsanordnung。

    公开(公告)号:EP0107355A2

    公开(公告)日:1984-05-02

    申请号:EP83305677.3

    申请日:1983-09-23

    申请人: FUJITSU LIMITED

    IPC分类号: G11C8/00

    摘要: A CMIS circuit device such as an IC chip of a semiconductor memory device which is made selectable by using at least two chip-select signals (CS,, CS 2 ) having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state and a chip-unselected state upon receiving the above-mentioned chip-select signals. The chip-select control circuit comprises a CMIS inverter means (IV,) for inverting one of the chip-select signals (CS 2 ) and a CMIS logic gate means (lV 2 ) for receiving an output signal (a) of the CMIS) inverter means and the other chip select signal or signals (CS 1 ) and for outputting an internal chip-select control signal (CS). The CMIS inverter means (IV 1 ) comprises a CMIS inverter (Q 20 , Q 21 ) and one or more control transistors (Q 19 ) which receive the other chip-select signal or signals (CS 1 ) at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.

    摘要翻译: CMIS电路装置,例如通过使用具有相反极性的至少两个芯片选择信号(CS1,CS2)可选择的半导体存储器件的IC芯片。 CMIS电路装置具有芯片选择控制电路,用于在接收上述芯片选择信号时建立芯片选择状态和芯片未选择状态。 芯片选择控制电路包括用于反转芯片选择信号(CS2)之一的CMIS反相器装置(IV1)和用于接收CMIS的反相器装置的输出信号(a)的CMIS逻辑门装置(IV2) 另一芯片选择信号(CS1)和用于输出内部芯片选择控制信号(CS)的芯片选择信号。 CMIS反相器装置(IV1)包括CMIS反相器(Q20,Q21)和一个或多个控制晶体管(Q19),其在其栅极处接收另一个芯片选择信号或CS1,并且串联插入到 CMIS逆变器的电源端子和电源。

    Semiconductor memory device
    27.
    发明公开
    Semiconductor memory device 失效
    半导体存储装置。

    公开(公告)号:EP0090590A2

    公开(公告)日:1983-10-05

    申请号:EP83301616.5

    申请日:1983-03-23

    申请人: FUJITSU LIMITED

    IPC分类号: G11C11/00 G11C7/00

    摘要: A semiconductor memory device such as a static-type random-access memory device comprising an address-change detection circuit which generates a pulse signal when an input address signal has changed and a latch circuit which temporarily stores the readout signal from a selected memory cell. The readout signal is input into the latch circuit in synchronization with the timing of the pulse signal or a short time after the pulse signal, and the readout data from the semiconductor memory device is obtained from the latch circuit, thereby increasing the time interval during which the readout data from the semiconductor memory device is available.

    Buffer circuit
    28.
    发明公开
    Buffer circuit 失效
    缓冲电路

    公开(公告)号:EP0055601A3

    公开(公告)日:1982-08-04

    申请号:EP81306073

    申请日:1981-12-23

    申请人: FUJITSU LIMITED

    IPC分类号: H03K19/017 H03K05/02

    摘要: n a buffer circuit comprising a first, a second and a third transistor (31, 32, 33) and a capacitor (4) for bootstrap action, an inverter (52) is connected to the output point (6) at which the second and third transistors are connected in series, the inverter inverting the output signal (Sout) and supplying the inverted signal (S52) to the gate of the first transistor (31), thereby to increase the rate of rise of the leading edge of an output signal pulse.

    Semiconductor resistor element
    29.
    发明公开
    Semiconductor resistor element 失效
    半导体电阻元件。

    公开(公告)号:EP0054471A2

    公开(公告)日:1982-06-23

    申请号:EP81401930.3

    申请日:1981-12-04

    申请人: FUJITSU LIMITED

    IPC分类号: H01L29/86 H01L27/06 H01L29/78

    摘要: A semiconductor resistor element comprising a semiconductor film (14) which has a desired shape and electrode wirings (20a-20b) at both ends thereof, and a control electrode (18) provided between the two ends of the semiconductor film (14) via an insulating film (16). The control electrode (18) is served with a control voltage which controls the resistance of the semiconductor film. Namely, the control electrode is served with a control voltage that changes with the change in temperature to offset the change in resistance of the semiconductor film caused by the change in temperature.