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公开(公告)号：EP0851235A3
公开(公告)日：1998-11-04
申请号：EP97310403.7
申请日：1997-12-22
发明人： Wong, Hing , Kirihata, Toshiaki , Krsnik, Bozidar
IPC分类号： G01R31/317 , G06F11/267
CPC分类号： G11C7/22 , G01R31/3016
摘要： A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.
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公开(公告)号：EP0851235A2
公开(公告)日：1998-07-01
申请号：EP97310403.7
申请日：1997-12-22
发明人： Wong, Hing , Kirihata, Toshiaki , Krsnik, Bozidar
IPC分类号： G01R31/317 , G06F11/267
CPC分类号： G11C7/22 , G01R31/3016
摘要： A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.
摘要翻译： 一种使用测试模式在集成电路中使用外部控制来控制内部信号的定时的电路和方法。 测试模式被设计为使得内部信号的时序来源于可以由测试器任意控制的外部控制。 只要在测试模式和集成电路的操作之间没有冲突，外部信号可以被施加到用于芯片控制的现有引脚。
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公开(公告)号：EP0766258A3
公开(公告)日：1997-11-05
申请号：EP96305900.1
申请日：1996-08-12
IPC分类号： G11C29/00
CPC分类号： G11C11/4091 , G06F2201/81 , G11C11/401 , G11C29/50
摘要： A bit line pair is coupled through a pair of high-resistance pass gates (164L,164R) to a sense amp (166). During sense, the high-resistance pass gates (164L,164R) act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp (166). A control circuit (185) selectively switches on and off bit line equalisation coincident with selectively passing either the equalisation voltage or set voltages to the sense amp (166) and an active sense amp load (172,174). Further, after it is set, the sense amp (166) is selectively connected to LDLs (182,184) through low-resistance column select pass gates (178,180). Therefore, the sense amp (166) quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp (166) to a second sense amplifier and off chip. After data is passed to the LDLs (182,184), the control circuit (185) enables the active sense amp load (172,174) to pull the sense amp high side to a full up level. Additionally, because the control circuit (185) uses the equalisation voltage to disable the sense amp (166), cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. The cell signal may be selected to determine both a high and a low signal margin.
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24.发明公开Isolation for electrical connection of stacked integrated semiconductor device structures 失效的半导体集成电路元件的层叠结构的电连接的绝缘
公开(公告)号：EP0767493A2
公开(公告)日：1997-04-09
申请号：EP96306640.2
申请日：1996-09-12
IPC分类号： H01L21/768 , H01L21/8242
CPC分类号： H01L27/10852 , H01L27/10808 , H01L2924/0002 , H01L2924/00
摘要： An improved method for isolating electrical conductors which are positioned over each other is disclosed. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. The method involves forming a recess in the upper surface of the lower conductor, and then at least partially filling the recess with an oxide-type material. This method is particularly valuable in the construction of stacked capacitor cells. Cells prepared using this technique also form part of this invention.
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25.发明公开Method of manufacturing an integrated circuit having p-MOSFETs with different channel widths 失效制造具有不同的信道宽度的p-沟道MOSFET的集成电路的方法
公开(公告)号：EP0694976A2
公开(公告)日：1996-01-31
申请号：EP95480068.6
申请日：1995-06-09
IPC分类号： H01L29/36 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/1095 , H01L27/0921 , H01L29/0642 , H01L29/1033 , H01L29/7838
摘要： An anomalous threshold voltage dependence on channel width measured on 0.25 µm ground rule generation trench-isolated buried-channel p-MOSFETs is used to enhance circuit performance. According to the invention, a set of transistors (100) having a source node (30), a drain node (40) and a common gate (20) can be constructed. Each of the N transistors in the set (10-1 to 10-N) has a channel width (Wn) chosen to provide the desired V t . The total number N is chosen to have the required current for the application in question. As the channel width is reduced, the magnitude of the threshold voltage first decreases before the onset of the expected sharp rise in V t for widths narrower than 0.4 µm. Modeling shows that a "boron puddle" is created near the trench bounded edge as a result of transient enhanced diffusion (TED) during the gate oxidation step, which imposes a penalty on the off-current of narrow devices. TED is governed by interstitials produced by a deep phosphorus implant, used for latchup suppression, diffusing towards the trench sidewall and top surface of the device.
摘要翻译： 信道宽度的异常的阈值电压的依赖关系的测量上12:25微米地面规则产生沟槽隔离埋沟道p MOSFET的用于增强电路的性能。 。根据具有源节点（30）本发明中，一组晶体管（100）的，漏极节点（40）和一个共同的栅极（20）可以被构造。 集合中的每个（10-1至10-N）的N个晶体管都具有选择以提供期望的Vt的沟道宽度（WN）。 总数N被选择为具有用于所讨论的应用所需的电流。 作为沟道宽度减小，阈值电压的幅度在第一Vt的预期急剧上升为宽度大于0.4微米的较窄的发病前降低。 模拟表明做了“硼熔池”在沟槽界定边缘作为在栅极氧化步骤，这就对窄器件的截止电流罚瞬态增强扩散（TED）的结果附近产生。 TED通过由深磷注入产生的填隙原子约束，用于闭锁抑制，朝向装置的沟槽侧壁和顶面扩散。
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