摘要:
The invention relates to a method for data transmission from and to a control unit (100), particularly an engine control unit for a motor vehicle, which has a first communication interface (110A) and a second communication interface (110B), having the following steps: the first communication interface (110A) is connected to a development tool (101), and the second communication interface (110B) is connected to one or more functional units during the development phase of the control unit (100); data are transmitted from the control unit (100) via the first communication interface (110A) to the development tool (101) using a first communication protocol; data are transmitted from the development tool (101) via the first communication interface (110A) to the control unit (100) using the first communication protocol; the connection between the first communication interface (110A) and the development tool (101) is broken; the first communication interface (110A) is connected to one or more further 20 functional units; and data are transmitted between the control unit (100) and the further functional unit(s) via the first communication interface (110A) using a second communication protocol.
摘要:
In order to detect a power outage in a volatile data memory containing useful data units and test data units associated with to the useful data units, the associated test data unit is read along with the useful data unit when said useful data unit is read-accessed, a decision is made as to whether the useful data is corrupt or not based on the test data unit, and a power outage is identified when at least two read useful data units within a predefined number of successive read accesses are considered to be corrupt.
摘要:
The invention relates to a motor vehicle control device, especially a motor control device (11), comprising a processor (12), a first interface (14) for communicating with functional units (16) of the motor vehicle and at least one second interface (17) which is combined with the processor (12) in a modular unit.
摘要:
Disclosed are a method and a device for monitoring an electronic circuit, in which all data of at least one memory can be successively read into and automatically verified in an ECC (error check and correction) unit that can be filled very quickly by the memory without all data having to be transmitted to a processor in a time-consuming process. The ECC testing range encompasses the data of several memory cells of said memory and can be configured as a multiple of the read-word range of the processor. An additional piece of data is formed regarding the data of a certain ECC testing range and can be stored in the memory, allowing the entire code/range of data of the at least one memory to be verified outside the various types of on-going instruction access by filling the entire ECC testing range of the ECC unit, including the additional piece of data, from the memory for each request issued by the processor for the content of a single memory cell. A piece of test data is formed from the data of the entire ECC testing range and is automatically compared with the piece of additional data stored in the ECC unit.
摘要:
The invention relates to a register arrangement, for a microcomputer, with a register (1), which comprises at least one register bit (R1 to Rn) and further storage media, dedicated to the register (1) and in which the data content of the register (1) may be temporarily stored. According to the invention, in order to reduce the processing time for recovery of the data content of the register (1) and to keep the silicon area necessary for the register arrangement to a minimum, the further storage media should be arranged as at least one shift register (2), with at least two shift register cells (S1 to Sm), whereby the content of any shift register cell (S1 to Sm) may be transferred to a register bit (R1 to Rn) and, vice versa, the content of a register bit (R1 to Rn) may be transferred to any shift register cell (S1 to Sm).
摘要:
The invention relates to a register arrangement, for a microcomputer, with a register (1), which comprises at least one register bit (R1 to Rn) and further storage media, dedicated to the register (1) and in which the data content of the register (1) may be temporarily stored. According to the invention, in order to reduce the processing time for recovery of the data content of the register (1) and to keep the silicon area necessary for the register arrangement to a minimum, the further storage media should be arranged as at least one shift register (2), with at least two shift register cells (S1 to Sm), whereby the content of any shift register cell (S1 to Sm) may be transferred to a register bit (R1 to Rn) and, vice versa, the content of a register bit (R1 to Rn) may be transferred to any shift register cell (S1 to Sm).
摘要:
The invention relates to an arrangement that consists of at least two microcontrollers (200, 300) on a common semiconductor substrate (100), each of the at least two microcontrollers (200, 300) having a hardware interface (210, 310), and the at least two microcontrollers (200, 300) being coupled to a coupling means (400) via the hardware interfaces (210, 310) for data-transmission.