公开(公告)号：EP4396818A1

公开(公告)日：2024-07-10

申请号：EP22865249.1

申请日：2022-06-28

申请人： Micron Technology, Inc.

发明人： JOHNSON, Bret Addison ,  CHOI, Jung-Hwa

IPC分类号： G11C11/4096 ,  G11C11/4074 ,  G11C7/10

CPC分类号： G11C11/4093 ,  G11C7/1057 ,  G11C29/028 ,  G11C29/021

公开(公告)号：EP3931830B1

公开(公告)日：2023-12-13

申请号：EP20715575.5

申请日：2020-02-28

发明人： SUH, Jungwon ,  CHUN, Dexter Tamio ,  LO, Michael Hawjing ,  THOZIYOOR, Shyamkumar ,  KUMAR, Ravindra

IPC分类号： G06F1/3234 ,  G06F1/3237 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/52 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50

公开(公告)号：EP4053840A1

公开(公告)日：2022-09-07

申请号：EP22160378.0

申请日：2010-12-01

申请人： Rambus Inc.

发明人： TSERN, Ely ,  VOGELSANG, Thomas ,  HAMPEL, Craig ,  BEST, Scott, C.

IPC分类号： G11C11/4074 ,  G11C11/4063 ,  G11C11/408 ,  G06F13/14 ,  G11C7/22 ,  G11C7/10

摘要： A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

公开(公告)号：EP4009179A3

公开(公告)日：2022-08-24

申请号：EP22153329.2

申请日：2018-05-11

申请人： Micron Technology, Inc.

发明人： BALLUCHI, Daniele ,  BLODGETT, Greg A ,  CARACCIO, Danilo ,  MIRICHIGNI, Graziano

IPC分类号： G06F13/16 ,  G06F1/32 ,  G06F1/3212 ,  G11C5/14 ,  G06F1/3234 ,  G06F11/30 ,  G06F1/18 ,  G06F1/30 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30 ,  G11C16/20

摘要： A method is disclosed comprising determining, by a host (102, 442), that a charge level of an energy source coupled to the host (102, 442) has fallen below a threshold value. The method further comprises transmitting, from the host (102, 442) to a memory device (104, 444) coupled to the host (102, 442), signaling indicative to turn power loss protection on for the memory device (104, 444), wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has fallen below the threshold value.

公开(公告)号：EP3433752B1

公开(公告)日：2022-05-04

申请号：EP16904230.6

申请日：2016-09-23

发明人： BRANDL, Kevin M. ,  HAMILTON, Thomas H.

IPC分类号： G06F13/16 ,  G11C5/14 ,  G06F15/78 ,  G11C11/406 ,  G11C5/04 ,  G11C11/4074 ,  G11C29/04

公开(公告)号：EP3703055A1

公开(公告)日：2020-09-02

申请号：EP20163498.7

申请日：2010-12-01

申请人： Rambus Inc.

发明人： TSERN, Ely ,  VOGELSANG, Thomas ,  HAMPEL, Craig ,  BEST, Scott, C.

IPC分类号： G11C11/4074 ,  G11C11/4063 ,  G11C11/408 ,  G06F13/14 ,  G11C7/22 ,  G11C7/10

摘要： A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

公开(公告)号：EP3648346A1

公开(公告)日：2020-05-06

申请号：EP19205742.0

申请日：2019-10-28

申请人： Commissariat à l'Energie Atomique et aux Energies Alternatives

发明人： BUCKLEY, Julien ,  MORVAN, Erwan

IPC分类号： H03F3/50 ,  H03F1/52 ,  G05F3/20 ,  H01L23/62 ,  H01L23/64 ,  G11C11/4074

摘要： L'invention a pour objet un circuit de polarisation d'un composant de puissance comprenant un pont diviseur capacitif et un pont diviseur résistif formés sur le même substrat que le composant. Une électrode additionnelle 1' en face avant 100 du substrat permet d'ajuster l'une des valeurs de capacité du pont capacitif en fonction de l'autre des valeurs de capacité issue de l'une des électrodes du composant de puissance. Le dimensionnement de cette électrode additionnelle permet en outre d'obtenir une résistance de fuite participant au pont diviseur résistif.
Alternativement, deux résistances additionnelles R, R' formées en face avant du substrat permettent d'obtenir le pont diviseur résistif indépendamment du pont diviseur capacitif.

公开(公告)号：EP3149733A4

公开(公告)日：2018-01-03

申请号：EP15800213

申请日：2015-05-14

申请人： MICRON TECHNOLOGY INC

发明人： MIRICHIGNI GRAZIANO ,  VILLA CORRADO

IPC分类号： G11C5/14 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30

CPC分类号： G11C5/144 ,  G06F13/1668 ,  G11C5/14 ,  G11C5/142 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30

摘要： The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

公开(公告)号：EP2399261B1

公开(公告)日：2013-11-20

申请号：EP10744195.8

申请日：2010-02-16

申请人： Lynch, John

发明人： Lynch, John

IPC分类号： G11C11/4074 ,  G11C11/4094 ,  G11C11/404 ,  G11C11/405 ,  G11C11/56

CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4099 ,  G11C11/565

摘要： Disclosed is a memory architecture comprising at least one memory bit cell and at least one read bit line whose voltage is controlled and changed by a current from a current controller. Each memory bit cell has a storage mechanism, a controlled current source, and a read switch. The controlled current source in each memory bit cell is electrically connected to the read bit line through the read switch. The current from the current controller that controls and changes the read bit line voltage flows through the controlled current source in the memory bit cell. The value of this current is determined by a function of a difference between the voltage on the storage mechanism in the memory bit cell and a reference voltage from a reference voltage input to the current controller. In some versions an indicator is provided for indicating when to stop the current in the controlled current source that controls a voltage change on one of the read bit lines. The indicator has an on and an off condition and a switch is provided for stopping the current in the controlled current source when the indicator is activated in the on condition. The current in the controlled current source is stopped when the voltage change on the read bit line is greater than a predetermined threshold.

公开(公告)号：EP2399261A4

公开(公告)日：2012-10-31

申请号：EP10744195

申请日：2010-02-16

申请人： LYNCH JOHN

发明人： LYNCH JOHN

IPC分类号： G11C11/4074 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4094 ,  G11C11/56

CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4099 ,  G11C11/565