公开(公告)号：EP1058309A1

公开(公告)日：2000-12-06

申请号：EP99830346.5

申请日：1999-06-04

申请人： STMicroelectronics S.r.l.

发明人： Dalla Libera, Giovanna ,  Vajana, Bruno ,  Patelmo, Matteo

IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/42324

摘要： The manufacturing process comprises the steps of: forming a first insulating region (25b) on top of an active area; forming a tunnel region (98) laterally to the first insulating region; forming a floating gate region (95); sealing the floating gate region with an insulating region (96; 34); forming a control gate region (43b) on top of the floating gate region; and forming conductive regions (65a, 65b) in the active area (14). The floating gate region (95) is obtained by depositing and defining a semiconductor material layer (27) through a floating gate mask (90). The floating gate mask (90) has an opening (92) with an internally delimiting side (90b) extending at a preset distance from a corresponding externally delimiting side (90a) of the mask, and the semiconductor material layer (27) is removed laterally at the external and internal delimiting sides so that the tunnel area (98) is defined, as regards its length, by the floating gate mask alone.

摘要翻译： 制造过程包括以下步骤：形成在有源区之上的第一绝缘区域（25B）; 形成隧道区域（98）晚反弹至第一绝缘区域; 形成浮置栅极区域（95）; 密封与所述浮置栅极区域在绝缘区（96; 34）; 形成在浮置栅极区域的顶部上的控制栅极区域（43B）; 以及形成导电区域（65A，65B）在有源区（14）。 浮置栅极区域（95）是通过沉积和限定通过浮置栅极掩模（90）的半导体材料层（27）中获得。 浮栅掩模（90）具有在开口（92），在内部限定侧（90b）的在预先设定的距离从相应的外部界定掩模侧（90A），和半导体材料层（27）被去除尾盘反弹扩展 在外部和内部侧面界定所以做了隧道区域（98）被定义，作为单独关于其长度，由浮动栅极掩模。

公开(公告)号：EP0996152A1

公开(公告)日：2000-04-26

申请号：EP98830644.5

申请日：1998-10-23

申请人： STMicroelectronics S.r.l.

发明人： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

IPC分类号： H01L21/8239 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546

摘要： The process permits the manufacture of LV transistors (80) with salicidated junctions on first areas (19) of a substrate (2), HV transistors (81) on second areas (14) and memory cells (82) on third areas (13). The process comprises the steps of: forming LV oxide regions (36) and LV gate regions (43a) on the first areas (19), HV oxide regions (34) on the second areas (14), selection oxide regions (34), tunnel oxide regions (26b) and matrix oxide regions (25b) on the third areas (13); forming floating gate regions (27b) and insulating regions (31b) on the tunnel oxide regions and the matrix oxide regions; forming first LV source and drain regions (55) laterally to the LV gate regions (43a); forming suicide regions (75a1, 75a2) on the first source and drain regions (55) and on the LV gate regions (43a); forming semiconductor material regions (43) completely covering the second and third areas (13, 14); and at the same time forming HV gate regions (43d) on the HV oxide regions, selection gate regions (43c) on the selection oxide regions and control gate regions (43b) on the insulating regions through a step of shaping the semiconductor material regions.

摘要翻译： 方法允许LV晶体管（80）与基板（2）的上第一区域salicidated结（19）的制造中，HV晶体管（81）上的第二区域（14）和存储单元上的第三区域（82）（13） ， 该方法包括以下步骤：形成LV氧化区（36）和LV栅极区域（43A）上的第一区域（19），在所述第二区域（14），选择氧化物区域HV氧化区（34）（34） 隧道氧化物区域（26B）和基质氧化物的区域（25B）在所述第三区域（13）; 形成浮栅区（27b）的与绝缘区域（31B）上的隧道氧化物区域和基体氧化物区; 形成第一LV源和漏区（55）尾盘反弹到LV栅极区域（43A）; 形成硅化物区（75A1，75A2）在所述第一源极和漏极区（55）和在LV栅极区域（43A）; 形成半导体材料区（43）完全覆盖所述第二和第三区域（13，14）; 和在在HV氧化物区域，选择栅区（43C）上的绝缘区域的选择氧化区和控制栅极区域（43B）通过成形半导体材料区域的步骤中同时形成HV栅极区（43D）。

公开(公告)号：EP0986107A1

公开(公告)日：2000-03-15

申请号：EP98830523.1

申请日：1998-09-08

申请人： STMicroelectronics S.r.l.

发明人： Vajana, Bruno ,  Dalla Libera, Giovanna

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/115

摘要： Cell array structure for an electrically erasable and programmable non-volatile memory device comprising an array of memory cells (1,2) arranged in rows (WL k ,WL k+1 ) and columns (BL i ,BL i+1 ) and grouped together in groups to form individually readable, programmable and erasable memory locations (BY1,BY2), each memory location having a respective control electrode (CGa,CGb) common to all the memory cells of the memory location. Conductor lines (100a,100b) directly contacting respective control electrodes of the memory locations are provided for externally selecting the control electrodes of the memory locations.

摘要翻译： 一种用于电可擦除和可编程的非易失性存储器件的电池阵列结构，包括排列成行（WLk，WLk + 1）和列（BLi，BLi + 1）的一组存储器单元（1,2） 形成单独可读，可编程和可擦除存储器位置（BY1，BY2），每个存储器位置具有对存储器位置的所有存储器单元共同的相应控制电极（CGa，CGb）。 提供与存储单元的各个控制电极直接接触的导体线（100a，100b），用于外部选择存储器位置的控制电极。

公开(公告)号：EP0975021A1

公开(公告)日：2000-01-26

申请号：EP98830444.0

申请日：1998-07-22

申请人： STMicroelectronics S.r.l.

发明人： Patelmo, Matteo ,  Galbiati, Nadia ,  Dalla Libera, Giovanna ,  Vajana, Bruno

IPC分类号： H01L21/8234 ,  H01L27/06

CPC分类号： H01L27/0629

摘要： The manufacture process comprises the following steps in succession: depositing a gate oxide layer on a silicon substrate (2) defining a transistor area (5) and a resistor area (6); depositing a multicrystal silicon layer (11) on the gate oxide layer (10); removing selective portions of the multicrystal silicon layer (11) to form a gate region (11a) over the transistor area (5) and a protective region (11b) completely covering the resistor area (6); forming source and drain regions (22) in the transistor area (5), laterally to the gate region (11a); forming silicide regions (25, 26 and 27) on and in direct contact with the source and drain regions (22), the gate region (11a) and the protective region (11b); removing selective portions of the protective region (11b) to form a delimitation ring (34); and implanting ionic dopants in the resistor area (6), inside the area defined by the protective ring (34), to form a lightly doped resistor (38) which has no silicide regions directly on it.

摘要翻译： 制造过程包括以下步骤连续：在硅衬底上沉积栅极氧化物层（2）的晶体管限定区域（5）和一个电阻器区（6）; 沉积栅极氧化物层上的多晶硅层（11）（10）; 去除多晶硅层（11）的选择部分以在所述晶体管区（5）和保护区域（11B）的栅极区（11A）完全覆盖调用该电阻区域（6）; 在晶体管区域中形成源和漏区（22）（5），晚反弹到栅极区域（11A）; 上，并在与所述源和漏区（22），所述栅极区域（11a）和所述保护区（11b）的直接接触形成硅化物区（25，26和27）; 去除保护区域（11B）的选择部分，以形成一个环划界（34）; 和植入在电阻区（6）的离子掺杂剂，由保护环（34）所限定的区域内部，以形成轻度掺杂的电阻器（38），其具有直接在其上没有形成硅化物区。

公开(公告)号：EP2034518A3

公开(公告)日：2009-06-03

申请号：EP08021768.0

申请日：1998-10-22

申请人： STMicroelectronics S.r.l.

发明人： Patelmo, Matteo ,  Galbiati, Nadia ,  Dalla Libera, Giovanna ,  Vajana, Bruno

IPC分类号： H01L27/105 ,  H01L27/088 ,  H01L27/115 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8247

CPC分类号： H01L21/823418 ,  H01L21/823443 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

摘要： An integrated electronic device with a silicon substrate (1) having low-voltage regions (19) and high-voltage regions (13) therein.
Low-voltage transistors (70) are in the LV regions and high-voltage transistors (71) are in the HV regions.
The transistors are different in respect of the silicidation of source and drain regions.
Each LV transistor has silicided source, gate and drain (55,57a1,57a2) and each HV transistor has silicided gate (57d) and non-silicided source and drain regions (64).

摘要翻译： 用具有低电压的区域（19）和高压区（13）在其中的硅衬底（1）的集成电子器件。 低电压晶体管（70）是在LV区域和高电压晶体管（71）是在HV区域。 晶体管处于相对于源和漏区的硅化的不同。 每个晶体管具有LV硅化源极，栅极和漏极（55,57a1,57a2），并且每个晶体管HV已硅化栅极（57D）和非硅化源和漏区（64）。

公开(公告)号：EP0975020B1

公开(公告)日：2009-02-11

申请号：EP98120033.0

申请日：1998-10-22

申请人： STMicroelectronics S.r.l.

发明人： Patelmo, Matteo ,  Galbiati, Nadia ,  Dalla Libera, Giovanna ,  Vajana, Bruno

IPC分类号： H01L21/8234 ,  H01L21/8239 ,  H01L27/105

CPC分类号： H01L21/823418 ,  H01L21/823443 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

公开(公告)号：EP1202353A1

公开(公告)日：2002-05-02

申请号：EP00830712.6

申请日：2000-10-27

申请人： STMicroelectronics S.r.l.

发明人： Vajana, Bruno ,  Patelmo, Matteo

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L27/02

CPC分类号： H01L27/11226 ,  H01L23/573 ,  H01L27/02 ,  H01L27/112 ,  Y10S257/922

摘要： A read only memory device, mask programmable during the fabrication of the device, comprises a plurality of memory cells formed onto a semiconductor substrate and organized in rows and columns to form an array of memory cells, the memory cells belonging to a same row sharing a common gate functioning as address wordline, each cell comprising a first region and a second region of type of conductivity opposite to that of the semiconductor substrate, a first dielectric layer formed on the plurality of memory cells, first contacts with the first regions of the cells through the first dielectric layer, connecting in common the first regions to a node of the device at a reference voltage, second contacts, each one established with a respective second region through the first dielectric layer and through a second dielectric layer formed on the first dielectric layer, and intercepted by a respective bitline.
Data stored in such a memory are made undecipherable by optical inspection if the second contacts are established with the second regions of only the memory cells programmed in a conductive state; interconnection contacts and false interconnection contacts are formed through the second dielectric layer, each geometrically above and in electrical continuity with one of the second contacts or geometrically above and in electrical discontinuity with one of the non contacted second regions of memory cells programmed in non conductive state; each bitline defined over the second dielectric layer, intercepting interconnection contacts and false interconnection contacts with the second regions of the cells belonging to a same column of the array.

摘要翻译： 在设备制造期间可编程的只读存储器件包括形成在半导体衬底上并以行和列组织以形成存储器单元阵列的多个存储器单元，属于同一行的存储器单元共享 公共栅极用作地址字线，每个单元包括与半导体衬底相反的导电类型的第一区域和第二区域，形成在多个存储单元上的第一介电层首先与单元的第一区域接触 通过第一电介质层，以参考电压将第一区域共同连接到器件的节点，第二触点，每个通过第一电介质层和通过形成在第一电介质上的第二介电层建立， 层，并被相应的位线拦截。 如果第二触点与只有存储器单元的第二区域被编程为导通状态而建立，则通过光学检查使存储在这种存储器中的数据不可修改; 互连触点和假互连触点通过第二介电层形成，每个第二电介质层在几何上在第二触点中的一个上方并且与第二触点中的一个导电连接，或者在非导通状态下编程的存储器单元的非接触的第二区域 ; 每个位线限定在第二介电层上，拦截互连触点和与属于该阵列的同一列的单元的第二区域的假互连接触。

公开(公告)号：EP1102319A1

公开(公告)日：2001-05-23

申请号：EP99830717.7

申请日：1999-11-19

申请人： STMicroelectronics S.r.l.

发明人： Vajana, Bruno ,  Patelmo, Matteo

IPC分类号： H01L27/105 ,  H01L21/8234 ,  H01L21/8239 ,  H01L27/088

CPC分类号： H01L27/11526 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546

摘要： For manufacturing an HV MOS transistor (80) having a low multiplication coefficient and a high threshold, a non-implanted area (6) of the substrate is used. This area thus has the same conductivity type and the same doping level as the substrate. The transistor is obtained by forming, over the non-implanted substrate area, a first gate region (43a) of semiconductor material having the same doping type as the non-implanted substrate area; and forming, inside the non-implanted substrate area, first source and drain regions (64a) of a second conductivity type, arranged at the sides of the first gate region (43a). At the same time, also a dual-gate HV MOS transistor (81) is formed, the source and drain regions (64b) of which are housed in a tub (13) formed in the substrate (2) and having the first conductivity type, but a higher concentration than the non-implanted substrate area. It is moreover possible to form a nonvolatile memory cell (82) simultaneously in a second tub (14) of the substrate (2) of semiconductor material.

摘要翻译： 为了制造具有低倍增系数和高阈值的HV MOS晶体管（80），使用衬底的非注入区域（6）。 因此该区域具有与衬底相同的导电类型和相同的掺杂水平。 通过在非注入衬底区域上形成具有与非植入衬底区域相同的掺杂类型的半导体材料的第一栅极区域（43a）来获得晶体管; 以及在所述非植入衬底区域内形成布置在所述第一栅极区域（43a）的侧面处的第二导电类型的第一源区和漏区（64a）。 同时，还形成了双栅极HV MOS晶体管（81），其源极和漏极区域（64b）容纳在形成于衬底（2）中的具有第一导电类型的桶（13）中 ，但是比非植入衬底区域更高的浓度。 此外，可以在半导体材料的基板（2）的第二槽（14）中同时形成非易失性存储单元（82）。

公开(公告)号：EP1058299A1

公开(公告)日：2000-12-06

申请号：EP99830347.3

申请日：1999-06-04

申请人： STMicroelectronics S.r.l.

发明人： Dalla Libera, Giovanna ,  Vajana, Bruno ,  Patelmo, Matteo

IPC分类号： H01L21/28 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42324

摘要： The manufacturing process comprises the steps of: forming a first insulating region (25b) on top of an active area; forming a tunnel region (98) at the side of the first insulating region; depositing and defining a semiconductor material layer (27) using a floating gate mask (90). In this way, a floating gate region (95) is formed. The floating gate mask (90) has an opening (92) having an internal delimiting side (90b) extending at a preset distance from a corresponding outer delimiting side (90a) of the mask, so that the floating gate region (95) forms inner a hole (97), and the tunnel area (98) is defined, as regards its length, by the floating gate mask alone. The hole (97) is filled with a dielectric material layer (103). Then, the surface of the floating gate region is planarized, and an insulating region (101) of dielectric material is made. Then a control gate region (43b) and conductive regions (65a, 65b) in the active area (14) are formed.

摘要翻译： 制造过程包括以下步骤：形成在有源区之上的第一绝缘区域（25B）; 形成在所述第一绝缘区域的一侧上的隧道区域（98）; 沉积并使用浮动栅极掩模（90）定义的半导体材料层（27）。 以这种方式，浮置栅极区域（95）形成。 浮栅掩模（90）具有在具有开口（92）在内部限定侧（90b）的在预先设定的距离从掩模的对应的外界定侧（90A）延伸，所以没有浮置栅极区域（95）形式的内部 一个孔（97），以及隧道区域（98）被定义，作为单独关于其长度，由浮动栅极掩模。 所述孔（97）填充有介电材料层（103）。 然后，浮置栅极区域的表面被平坦化，并以绝缘介电材料的区域（101）制成。 然后控制栅极区域（43B）和导电区域（65A，65B）在有源区（14）形成。

公开(公告)号：EP1024527A2

公开(公告)日：2000-08-02

申请号：EP99126235.3

申请日：1999-12-30

申请人： STMicroelectronics S.r.l.

发明人： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

IPC分类号： H01L21/8246 ,  H01L21/8247

CPC分类号： H01L27/112 ,  G11C11/56 ,  G11C11/5692 ,  H01L27/11293

摘要： Presented is a method for obtaining a multi-level ROM in a dual gate EEPROM process flow. The method begins with, on a semiconductor substrate, defining active areas respectively for transistors of ROM cells, transistors of electrically erasable non-volatile memory cells, and additional transistors of the storage circuitry. Then, integrated capacitors are integrated in the storage circuit. According to this method, during the implanting step for forming integrated capacitors, at least an active area of the ROM cell is similarly implanted.

摘要翻译： 提出了一种在双栅极EEPROM工艺流程中获得多级ROM的方法。 该方法开始于在半导体衬底上分别定义用于ROM单元的晶体管，电可擦除非易失性存储单元的晶体管和存储电路的附加晶体管的有源区。 然后，集成电容器集成在存储电路中。 根据该方法，在用于形成集成电容器的注入步骤期间，类似地植入ROM单元的至少一个有效区域。