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    ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS
    21.
    发明授权
    ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS 失效
    ARCHITEKTUR-UND BESCHALTUNGSSCHEMAFÜRPROGRAMMIERBARE LOGISCHE SCHALTUNGEN

    公开(公告)号：EP0712548B1

    公开(公告)日：2003-04-02

    申请号：EP94922455.4

    申请日：1994-06-24

    申请人： BTR, INC.

    发明人： TING, Benjamin, S.

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

    摘要： An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. A uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. A uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.

    摘要翻译： 一种可编程逻辑电路，包括：用于向可编程逻辑电路输入信号的输入/输出接口（102） 耦合到所述输入/输出接口的多个单元，每个所述单元能够对信号执行数字处理; 第一组路由线，用于耦合多个小区以形成小区的逻辑群集（107），所述第一组路由线路还向小区或其他逻辑群集提供可编程联接; 第二组路由线（108），用于耦合多个逻辑簇以形成逻辑的小区集群的逻辑块，其中每个小区可编程地耦合到所述第二组路由线; 以及多组高级全局路由线，跨越多个逻辑块的每组全局路由线，其中每组较高级全局路由线可编程地耦合到第二组路由线，所述第一组 通过第二组路由线路由线路和单元。

    Programmable logic array integrated circuits
    24.
    发明公开
    Programmable logic array integrated circuits 失效
    Progammierbare，integrierte Logikanordnung

    公开(公告)号：EP1134896A2

    公开(公告)日：2001-09-19

    申请号：EP01112375.9

    申请日：1992-08-06

    申请人： Altera Corporation

    发明人： Pederson, Bruce B. ,  Cliff, Richard G. ,  Ahanin, Bahram ,  Lytle, Craig Schilling ,  Heile, Francis B. ,  Veenstra, Kerry Scott

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

    摘要： A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

    摘要翻译： 可编程逻辑阵列集成电路具有被分组成多个相互排斥的组的多个可编程逻辑元件。 每组包括与该组唯一相关联的信号导体，用于在该组中的可编程逻辑元件之间传送信号。 提供其他信号导体用于在组之间传送信号。 多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。

    FIELD PROGRAMMABLE GATE ARRAY (FPGA) WITH INTERCONNECT ENCODING
    26.
    发明授权
    FIELD PROGRAMMABLE GATE ARRAY (FPGA) WITH INTERCONNECT ENCODING 失效
    现场可编程门阵列（FPGA）有编码VERBINDUNDSSTRUKTUR

    公开(公告)号：EP0830735B1

    公开(公告)日：2000-11-08

    申请号：EP96918445.6

    申请日：1996-06-07

    申请人： ADVANCED MICRO DEVICES INC.

    发明人： SHARPE-GEISLER, Bradley, A.

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17748 ,  H03K19/17704 ,  H03K19/17736

    摘要： A method of programming an FPGA to enable encoding of configuration logic block (CLB) outputs enabling an efficient use of FPGA routing resources. The method of the present invention utilizes the one hot approach, wherein only one CLB output is high at a time, to form a state machine using an FPGA. To provide encoding, programmable interconnect points (PIPs) may be programmed to connect CLB outputs to interconnect lines so that the interconnect lines indicate states of the CLB outputs in an encoded form. To provide such encoding, less interconnect lines than CLB outputs provide the encoded form of the CLB outputs. Thus, PIPs can connect a single interconnect line to more than one CLB output. Further, PIPs can connect a single CLB output to interconnect lines provided in separate parallel routing paths. To prevent erroneous results, CLB outputs which are not hot are tri-stated. Output decoding can be provided by an additional decoder in the FPGA connected to the interconnect lines providing the encoded form of the CLB outputs. Output decoding may alternatively be provided using a CLB.

    METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE
    27.
    发明公开
    METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE 失效
    VERFAHREN UND VORRICHTUNGFÜREINE UNIVERSELLE PROGRAMMGESTEUERTE BUSARCHITEKTUR

    公开(公告)号：EP0941579A1

    公开(公告)日：1999-09-15

    申请号：EP97939805.0

    申请日：1997-09-04

    申请人： BTR, INC.

    发明人： PANI, Peter, M. ,  TING, Benjamin, S.

    IPC分类号： G06F13 ,  H03K19

    CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17796

    摘要： The system and method of the present invention provides an innovative bus system of lines (705) which can be programmed and to provide data, control and address information to the logic circuits (701-702) interconnected by the bus system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits, such as megacells (701-702). The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i.e., wide, deep or both) and the sharing of common lines for system level communication.

    摘要翻译： 本发明的系统和方法提供了一种创新的线路总线系统（705），其可以被编程并且向由总线系统互连的逻辑电路（701-702）提供数据，控制和地址信息。 这种灵活的结构和过程使得能够创建可配置系统以可编程地连接一个或多个逻辑电路，例如大型电力（701-702）。 总线系统的可编程性使得能够以任意方式（即，宽，深或两者）级联多个兆字节，并且共享用于系统级通信的公共线路。

    Programmable logic architecture incorporating a content addressable embedded array block
    28.
    发明公开
    Programmable logic architecture incorporating a content addressable embedded array block 审中-公开
    可编程逻辑架构与嵌入的内容可寻址阵列块

    公开(公告)号：EP0913944A2

    公开(公告)日：1999-05-06

    申请号：EP98309004.4

    申请日：1998-11-03

    申请人： Altera Corporation

    发明人： Veenstra, Kerry ,  Heile, Francis B.

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1776 ,  G11C7/1045 ,  G11C15/00 ,  H03K19/17704 ,  H03K19/17736

    摘要： The invention relates to an integrated circuit that can be configured to operate as a content addressable memory. The integrated circuit includes a first functional block that stores at least one keyword dataword which is associated with a group of associated data words. The integrated circuit also includes a second functional block that stores the group of associated datawords. The second functional block is connected to the first functional block in such a way that if a request dataword received at the first functional block matches at least one keyword dataword stored therein, then an associated result dataword included in the group of associated data words stored in the second functional block is output by the second functional block. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD).

    Non-disruptive, randomly addressable memory system
    30.
    发明公开
    Non-disruptive, randomly addressable memory system 失效
    不间断可选自由存取存储器系统

    公开(公告)号：EP0877385A3

    公开(公告)日：1999-03-03

    申请号：EP98112802.8

    申请日：1993-07-01

    申请人： CAMAROTA, Rafael, C.

    发明人： CAMAROTA, Rafael, C.

    IPC分类号： G11C13/00 ,  H03K19/177

    CPC分类号： H03K19/17752 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/1776

    摘要： An apparatus and method for reprogramming a reconfigurable-logic array is provided whereby a portion of the array (15) can be reconfigured without disrupting the operation of the entire array. Avoiding total disruption of array operation typically requires that the configuration controls signals, which determine the configuration of the array, remain substantially non-disrupted during a reprogramming operation. In one embodiment, the reprogramming operates by unique decoding in which an electrical path (12) is established only between the particular storage elements being reprogrammed, thereby avoiding disruption of the configuration control signals provided by other storage elements. In other embodiments, buffers and/or read-modify-write techniques are used to minimize disruption of configuration control signals of storage elements not being reprogrammed.