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公开(公告)号：EP2329594A1
公开(公告)日：2011-06-08
申请号：EP09812522.2
申请日：2009-09-08
发明人： THOMAS, Clive
CPC分类号： H03F1/22 , H03F1/32 , H03F3/183 , H03F3/3016 , H03F3/3022 , H03F2200/03
摘要： An audio amplifier circuit has a first cascode stage configured as a voltage gain stage and having an input for an audio signal, and an output. The circuit has a second cascode stage configured as a unity gain or near unity gain stage and having an input to receive an output from the first cascode stage, and a low impedance output to drive an output stage of an audio power amplifier. The first cascode stage has a first, input transistor having an input biased to a predetermined bias voltage, and a second, output transistor arranged to drive the second cascode stage. The first, input transistor of the first cascode stage may have a common-emitter configuration, and the second, output transistor may have a common-base configuration. The invention extends to an audio amplifier which includes a circuit of the invention.
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公开(公告)号：EP2284989A2
公开(公告)日：2011-02-16
申请号：EP10007399.8
申请日：2010-07-16
申请人： Vivant Medical, Inc.
发明人： Behnke, Robert J.
CPC分类号： H03F1/0233 , H03F3/19 , H03F3/26
摘要： Disclosed is an apparatus and method for operating a microwave amplifier (140) with improved efficiency and reduced harmonic emissions. The disclosed amplifier includes a variable rail voltage supply (120) and a variable input drive stage (130). A controller (110) continually monitors the amplifier output and adjusts the rail voltage and input drive signal to achieve high efficiency and low harmonic emissions. The amplifier may include a dynamic bias controller configured to operate the gain elements outside the linear region. Efficiencies of over 70% may be achieved by the disclosed amplifier.
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公开(公告)号：EP1149466B1
公开(公告)日：2011-01-26
申请号：EP00969308.6
申请日：2000-09-25
申请人： NXP B.V.
摘要： The invention relates to an amplifier comprising a cascade circuit including an input circuit, a cascode circuit and an output circuit. The input circuit receives input signals via an input (10), which input signals are converted to amplified signals by the cascode circuit. These amplified signals are subsequently supplied to an output (94) by the output circuit. The cascode circuit comprises two input transistors (40 and 62) and an output transistor (74). By means of three capacitors (32, 46 and 50) and a coil (48), the cascode circuit is built up in such a way that the input transistors (40 and 62) are parallel-connected for comparatively high-frequency input signals, while the input transistors (40 and 62) are series-connected for comparatively low-frequency supply signals. This results in the transconductance being doubled, while the DC collector current or drain current remains the same. By doubling the transconductance, the contribution of the cascode circuit to the intermodulation distortion in the amplified signals is reduced substantially. As the DC collector current or drain current remains unchanged, the power dissipated in the amplifier remains substantially the same.
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公开(公告)号：EP1787388A4
公开(公告)日：2010-12-15
申请号：EP05773277
申请日：2005-07-18
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25.发明公开Methods and apparatus for switching between class A and A/B operation in a power amplifier 有权类之间切换的功率放大器的操作和A / B类操作的方法和装置
公开(公告)号：EP1777814A2
公开(公告)日：2007-04-25
申请号：EP06076871.0
申请日：2006-10-12
CPC分类号： H03F3/26 , H03F1/0261 , H03F3/02 , H03F3/181 , H03F3/20 , H03F3/211 , H03F3/28 , H03F3/30 , H03F2200/27 , H03F2200/421 , H03F2200/541 , H03F2203/21145
摘要： Method and apparatus contemplate: an output transformer (T108) having at least first (112A) and second (112B) separate primary windings and at least one secondary winding (114), each winding including a first (in phase) end and a second (out of phase) end; at least first and second active elements (104A,104B), each having at least a pair of power terminals and a control terminal, one power terminal of each active element being coupled to a common node; and a switching circuit (106) operable to change a circuit configuration of the first and second primary windings and the active elements between a class A mode and a class A/B mode.
摘要翻译： 方法和装置，设想了：具有至少第一（112A）的输出变压器（T108）和第二（112B），单独的初级绕组和至少一个次级绕组（114），每个绕组包括第一（（同相）端部和第二 出相位）端的; 至少第一和第二有源元件（104A，104B），每一个具有至少一对电源端子和控制端子，被耦合到公共节点的每个有源元件的一个电源端子; 和开关电路（106），可操作以改变所述第一和第二初级绕组和一类A模式和A / B类模式之间的有源元件的电路结构。
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26.发明公开Class B amplifier with process variation independent deadband 审中-公开Class-B-Verstärkermit Totzone，welcheunabhängigvon einer Prozessvariation ist
公开(公告)号：EP1655833A1
公开(公告)日：2006-05-10
申请号：EP04368069.3
申请日：2004-11-03
发明人： Kronmueller, Frank
CPC分类号： H03F3/265 , H03F3/45183
摘要： A class B amplifier circuit produces a deadband that is independent of semiconductor process variations and creates a positive voltage when a differential input voltage is non-zero. A differential input amplifier couples differential currents representing the differential input voltage to a logarithmic compression circuit, which in turn creates an output voltage that is a function of the differential input voltage and is independent of semiconductor process variations. Transistor devices in the differential amplifier and the logarithmic compression circuit are biased in the non-saturated region of a transistor transfer curve in a weak inversion state. A combination of two comparator circuits compares the output voltage to a reference voltage to create a combined output voltage that is a positive when the input is non-zero.
摘要翻译： B类放大器电路产生与半导体工艺变化无关的死区，当差分输入电压不为零时，产生正电压。 差分输入放大器将表示差分输入电压的差分电流耦合到对数压缩电路，对数压缩电路又产生作为差分输入电压的函数的输出电压，并且与半导体工艺变化无关。 差分放大器和对数压缩电路中的晶体管器件在弱反转状态下被偏置在晶体管传输曲线的非饱和区域中。 两个比较器电路的组合将输出电压与参考电压进行比较，以产生当输入为非零时为正的组合输出电压。
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公开(公告)号：EP1088391A4
公开(公告)日：2004-11-24
申请号：EP00928172
申请日：2000-04-14
申请人： THAT CORP
发明人： FLORU FRED
CPC分类号： H03F3/3076 , H03F3/3071
摘要： The present invention is directed to a buffer stage for buffering and isolating a signal source from an external load. The stage has a signal input terminal for receiving an input signal from said signal source and a signal output terminal for providing an output signal (OUTPUT), corresponding to said input signal (INPUT), to said external load. The stage comprises: an input section (102) including at least two driver transistors (Q3 and Q4) each arranged so as to operate with a predetermined bias current; an output section (106) including at least two output transistors (Q1 and Q2) each arranged so as to operate with a predetermined quiescent current a voltage source, coupled to the input and output sections and constructed and arranged so as to set the quiescent currents flowing through the output transistors (Q1 and Q2) substantially independent of the size of the bias current flowing through the driver transistors (Q3 and Q4).
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公开(公告)号：EP1400012A2
公开(公告)日：2004-03-24
申请号：EP01986805.8
申请日：2001-10-09
发明人： AOKI, IchiroCalifornia Institute of Technology , HAJIMIRI, S.A.California Institute of Technology , RUTLEDGE, DavidCalifornia Institute of Technology
CPC分类号： H03F1/223 , H03F3/265 , H03F3/423 , H03F3/604 , H03F2200/534 , H03F2200/537 , H03F2200/541
摘要： The present invention discloses a distributed power amplifier topology and device that efficiently and economically enhances the power output of an RF signal to be amplified. The power amplifier comprises a plurality of push-pull amplifiers interconnected in a novel circular geometry that preferably function as a first winding of an active transformer having signal inputs of adjacent amplification devices driven with an input signal of equal magnitude and opposite phase. The topology also discloses the use of a secondary winding that matches the geometry of primary winding and variations thereof that serve to efficiently combine the power of the individual power amplifiers. The novel architecture enables the design of low-cost, fully-integrated, high-power amplifiers in the RF, microwave, and millimeter-wave frequencies.
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公开(公告)号：EP0923194A3
公开(公告)日：2002-10-30
申请号：EP98309973.0
申请日：1998-12-04
申请人： Korg Inc.
发明人： Mori, Yasuhiko , Mieda, Fumio , Mitoma, Hirofumi
CPC分类号： H03F3/20 , H03F3/26 , H03F5/00 , H03F2200/03 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2200/549
摘要： Output signals given from a tube amplifier (5) are amplified by a small number of vacuum tubes with maintaining the output property of the output signals. A second circuit (C2) is arranged in parallel to a first circuit (C1) wherein the output signals given from a vacuum tube (VA1) is flowing, and a node of the first circuit (C1) and the second circuit (C2) is connected to an input terminal of an output transformer (TR(1)). Since electric current proportioned to current level flowing in the first circuit (C1) flows into the second circuit (C2), current which amplified the output signals given from the vacuum tube (VA1) flows into the primary side of the output transformer (TR(1)). Consequently, by using the tube amplifier containing the small number of vacuum tubes, it is possible to obtain high output power as if it is obtainable by using a large number of vacuum tubes.
摘要翻译： 由管放大器（5）给出的输出信号由少量真空管放大，保持输出信号的输出特性。 第二电路（C2）与从真空管（VA1）输出的输出信号流动的第一电路（C1）平行布置，第一电路（C1）和第二电路（C2）的节点为 连接到输出变压器（TR（1））的输入端子。 由于与在第一电路（C1）中流动的电流水平成比例的电流流入第二电路（C2），所以放大从真空管（VA1）给出的输出信号的电流流入输出变压器的初级侧（TR（ 1））。 因此，通过使用包含少量真空管的管放大器，可以获得高输出功率，就好像通过使用大量真空管可获得的那样。
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30.发明公开Differential amplifier and a method of compensation 审中-公开Differenzverstärkerund Kompensationsverfahren
公开(公告)号：EP0917284A3
公开(公告)日：2001-08-22
申请号：EP98121491.9
申请日：1998-11-12
申请人： NEC CORPORATION
摘要： In a differential amplifier that is formed by a first differential amplifier formed by a first FET (MP1), to which a first input is applied, and a second FET (MP2), to which a second input is applied, a second differential amplifier formed by a third FET (MP7), to which the first input is applied, and a fourth FET (MP8), to which the second input is applied, in which each load of the first differential amplifier and the second differential amplifier being formed by a current mirror circuit, the signal to be fed to a subsequent stage is extracted from the drain D of the first FET (MP1) or the second FET (MP2).
摘要翻译： 在由施加有第一输入的第一FET（MP1）和施加了第二输入的第二FET（MP2）形成的第一差分放大器形成的差分放大器中，形成第二差分放大器 通过施加第一输入的第三FET（MP7）和施加第二输入的第四FET（MP8），其中第一差分放大器和第二差分放大器的每个负载由 电流镜电路，从第一FET（MP1）或第二FET（MP2）的漏极D提取要馈送到后级的信号。
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