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2021 条记录 (耗时 0.021 秒)

    FEED-FORWARD CURRENT COMPENSATION FOR CMOS SIGNAL PATH
    25.
    发明公开
    FEED-FORWARD CURRENT COMPENSATION FOR CMOS SIGNAL PATH 审中-公开

    公开(公告)号：EP3789843A1

    公开(公告)日：2021-03-10

    申请号：EP20189518.2

    申请日：2020-08-05

    申请人： Semtech Corporation

    发明人： NUTTGENS, Jonah Edward

    IPC分类号： G05F1/10 ,  G05F1/56 ,  G05F1/565 ,  G05F1/577 ,  H02M1/15 ,  H02M3/07 ,  H02M1/00 ,  H03K17/042 ,  H03K17/16 ,  H03K19/003

    摘要： An integrated circuit has a CMOS signal path (100) coupled for receiving a data signal (data-in, data-in/). A compensation circuit (195) is coupled to a power supply rail (Vreg, ground) of the CMOS signal path for injecting a compensation current (Icomp) into the power supply rail. The compensation circuit can be a charge pump (fig. 2: 150) operating in response to the data signal to inject the compensation current (Icomp) into the power supply rail each transition of the data signal. The compensation circuit can be a replica CMOS signal path (fig. 3: 195) to inject the compensation current (Icomp) into the power supply rail (Vreg) each transition of the data signal. The compensation circuit can be a voltage regulator (fig. 4: 212) and current mirror (fig. 4: 220, 226) including an input coupled to the voltage regulator. The replica CMOS signal path (fig. 4: 236, 242) receives an operating potential (node 218) from the voltage regulator. An output of the current mirror injects the compensation current (fig. 4: Icomp) into the power supply rail (fig. 4: Vreg) each transition of the data signal.

    IMMEDIATE FAIL DETECT CLOCK DOMAIN CROSSING SYNCHRONIZER
    28.
    发明公开
    IMMEDIATE FAIL DETECT CLOCK DOMAIN CROSSING SYNCHRONIZER 审中-公开

    公开(公告)号：EP3761508A2

    公开(公告)日：2021-01-06

    申请号：EP20183511.3

    申请日：2020-07-01

    申请人： STMicroelectronics International N.V.

    发明人： GOYAL, Avneep Kumar

    IPC分类号： H03K5/135 ,  H03K19/003 ,  H04L7/00

    摘要： A synchronizer circuit (300A) includes a first synchronizer (306A) having a first input (A) for receiving a signal associated with a first clock signal (CLK_A), a second input for receiving a second clock signal (CLK_B), and an output (Z1) for providing a synchronizer circuit output signal (SYNCH_O/P); a second synchronizer (308A) having a first input for receiving the signal associated with the first clock signal (CLK_A), a second input for receiving the second clock signal (CLK_B), and an output (Z2); a detection stage (310A) having a first input coupled to the output of the first synchronizer (306A) and to the output of the second synchronizer (308A), a second input for receiving the second clock signal (CLK_B), and an output (Z4); and a fault output stage (312A) having a first input (Z4) coupled to the detection stage (310A), a second input for receiving the second clock signal (CLK_B),, and an output for providing a fault output signal (FAULT_O/P).

    ASSOCIATION DE TRANSISTORS EN SÉRIE
    30.
    发明公开
    ASSOCIATION DE TRANSISTORS EN SÉRIE 审中-公开

    公开(公告)号：EP3731414A1

    公开(公告)日：2020-10-28

    申请号：EP20171008.4

    申请日：2020-04-23

    申请人： STMicroelectronics (Rousset) SAS

    发明人： FROIDEVAUX, Nicolas ,  LOPEZ, Laurent

    IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K17/30

    摘要： La présente description concerne un dispositif comportant, en série (71) :
    un premier transistor (73) MOS de type P ;
    un deuxième transistor (75) MOS de type N, connecté au premier transistor (71) ; et
    un troisième transistor (77), connecté au deuxième transistor (75), ledit troisième transistor (77) étant commandé par un signal numérique,
    dans lequel la grille (733) du premier transistor (73) et la grille (753) du deuxième transistor (75) sont interconnectées et destinées à recevoir un potentiel (VDD) d'alimentation d'une puce.