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公开(公告)号：EP3992646A1
公开(公告)日：2022-05-04
申请号：EP21202658.7
申请日：2021-10-14
申请人： STMicroelectronics International N.V. , STMicroelectronics Application GmbH , STMicroelectronics S.r.l.
IPC分类号： G01R31/317 , G06F1/04 , G06F11/16 , G06F11/273 , G11C7/22
摘要： A testing tool (10) includes a clock generation circuit (16, 18, 22) generating a test clock (Tck) and outputting the test clock via a test clock output pad (31), data processing circuitry (19) clocked by the test clock, and data output circuitry (20) receiving data output from the data processing circuitry and outputting the data via an input/output, IO pad (32), the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit (41) generating a delayed version of the test clock (DELAYED_TCK), and data input circuitry (21) receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock (DELAYED_TCK). The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer (50) and receipt of the data input from the external computer via the IO pad.
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公开(公告)号：EP4432091A1
公开(公告)日：2024-09-18
申请号：EP24159922.4
申请日：2024-02-27
IPC分类号： G06F11/22 , G06F11/36 , G01R31/28 , G06F11/263 , G06F11/273
CPC分类号： G06F11/263 , G06F11/273 , G06F11/2733 , G06F11/2247 , G01R31/2851 , G06F11/3656 , G01R31/31701 , G01R31/31705 , G01R31/31712 , G01R31/31722
摘要： A system (300) is provided that includes a debugging tool (302) and an application board (304). The debugging tool includes a serial wire debug, SWD, host (106) coupled to a single signal debug port, SSDP, host (308). The application board includes an SWD target (108) coupled to an SSDP target (316). The SWD target is configured to communicate SWD signals with the SWD host. The SSDP target is configured to encode the SWD signals to SSDP signals for communication over a Controller Area Network, CAN, Bus (322) between the application board and the debugging tool. The SSDP signals are pulse-width modulation, PWM, encoded signals of the SWD signals. An SWD clock signal generated by the SWD host is the carrier signal for the PWM encoded signals. The SSDP target is configured to decode the SSDP signals received from the SSDP host over the CAN Bus to the SWD signals.
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公开(公告)号：EP4404065A1
公开(公告)日：2024-07-24
申请号：EP23220123.6
申请日：2023-12-22
CPC分类号： G06F11/3648 , G06F11/3636 , G06F11/1441
摘要： An apparatus (100) comprises debug circuitry (104) configured to perform debug operations on a processing system (106), and reset circuitry (102) configured to generate a trace and debug reset signal (110) and a main reset signal (112) based at least in part on an invoke reset signal (108). The main reset signal (112) is communicated to elements of the processing system (106), and the trace and debug reset signal (110) is communicated to elements of the debug circuitry (104).
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公开(公告)号：EP4174692A1
公开(公告)日：2023-05-03
申请号：EP22201273.4
申请日：2022-10-13
摘要： A system on a chip including a first-port controller (106) for a first development port (102) configured to receive a first development tool and a second-port controller (108) for a second development port (104) configured to receive a second development tool. The system on a chip further including a central controller (110) in communication with the first-port controller (106), the second-port controller (108), and a security subsystem (112). The central controller (110) being configured to manage authentication exchanges between the security subsystem (112) and the first development tool and authentication exchanges between the security subsystem (112) and the second development tool.
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5.发明公开
公开(公告)号：EP4404514A1
公开(公告)日：2024-07-24
申请号：EP24305035.8
申请日：2024-01-09
发明人： GOYAL, Avneep Kumar , GUION, Nicolas , SINGHAL, Sumit Kumar , SINGH, Jagtar , KUMAR, Dhulipalla Phaneendra
IPC分类号： H04L12/40 , G06F9/54 , G06F13/38 , H04L47/30 , H04L47/34 , H04L49/90 , H04L67/12 , H04L69/18 , H04L1/00
CPC分类号： H04L12/40 , H04L2012/4021520130101 , H04L12/40032 , H04L12/40013 , H04L2001/009420130101 , H04L69/18 , H04L47/30 , H04L47/34 , H04L49/90 , G06F13/385 , G06F9/546 , H04L67/125 , H04L69/321
摘要： Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.
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6.发明公开
公开(公告)号：EP4339783A1
公开(公告)日：2024-03-20
申请号：EP23193443.1
申请日：2023-08-25
摘要： A processing system (200) includes: main (202a) and shadow (202b) processing cores configured to operate in lockstep based on a core clock (CLK core ). The main processing core (202a) includes a main functional core (308a) and a main debug circuit (206a). The shadow processing core (202b) includes a shadow functional core (308b) and a shadow debug circuit (206b). A redundancy checker circuit (208) is configured to assert an alarm signal (S alarm ) when a discrepancy between outputs from the main (308a) and shadow (308b) functional cores is detected. A debug bus synchronizer circuit (212) is configured to receive input debug data in synchrony with a debug clock (CLK debug ), and provide synchronized debug data in synchrony with the core clock (CLK core ) to a debug bus (232) based on the input debug data, where the main (206a) and shadow (206b) debug circuits are configured to receive the synchronized debug data in synchrony with the core clock (CLK core ) from the debug bus (232), and where the debug clock (CLK debug ) is asynchronous with respect to the core clock (CLK core ).
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公开(公告)号：EP3761508A2
公开(公告)日：2021-01-06
申请号：EP20183511.3
申请日：2020-07-01
发明人： GOYAL, Avneep Kumar
IPC分类号： H03K5/135 , H03K19/003 , H04L7/00
摘要： A synchronizer circuit (300A) includes a first synchronizer (306A) having a first input (A) for receiving a signal associated with a first clock signal (CLK_A), a second input for receiving a second clock signal (CLK_B), and an output (Z1) for providing a synchronizer circuit output signal (SYNCH_O/P); a second synchronizer (308A) having a first input for receiving the signal associated with the first clock signal (CLK_A), a second input for receiving the second clock signal (CLK_B), and an output (Z2); a detection stage (310A) having a first input coupled to the output of the first synchronizer (306A) and to the output of the second synchronizer (308A), a second input for receiving the second clock signal (CLK_B), and an output (Z4); and a fault output stage (312A) having a first input (Z4) coupled to the detection stage (310A), a second input for receiving the second clock signal (CLK_B),, and an output for providing a fault output signal (FAULT_O/P).
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公开(公告)号：EP4174659A1
公开(公告)日：2023-05-03
申请号：EP22201300.5
申请日：2022-10-13
申请人： STMicroelectronics Application GmbH , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
摘要： A trace-data preparation circuit (300) including a filtering circuit (302) to receive traced memory-write data and a First In First Out buffer (306) coupled with the filtering circuit (302) to receive selected memory-write data filtered by the filtering circuit (302). The trace-data preparation circuit may further include a data compression circuit (308) to provide packaging data to a packaging circuit (310) that groups the selected memory-write data.
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公开(公告)号：EP4033665A3
公开(公告)日：2022-11-09
申请号：EP22150368.3
申请日：2022-01-05
发明人： GOYAL, Avneep Kumar
IPC分类号： H03K19/003 , G06F11/16
摘要： An apparatus (100) includes a main core processor (102) configured to receive a first signal through a first main buffer (111), a second signal through a second main buffer (121), a third signal through a third main buffer (131) and a fourth signal through a fourth main buffer (141), a shadow core processor (104) configured to receive the first signal through a first shadow buffer (211), the second signal through a second shadow buffer (221), the third signal through a third shadow buffer (231) and the fourth signal through a fourth shadow buffer (241), and a first glitch suppression buffer (115) coupled to a common node of an input of the first main buffer (111) and an input of the first shadow buffer (211).
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公开(公告)号：EP4033665A2
公开(公告)日：2022-07-27
申请号：EP22150368.3
申请日：2022-01-05
发明人： GOYAL, Avneep Kumar
IPC分类号： H03K19/003
摘要： An apparatus (100) includes a main core processor (102) configured to receive a first signal through a first main buffer (111), a second signal through a second main buffer (121), a third signal through a third main buffer (131) and a fourth signal through a fourth main buffer (141), a shadow core processor (104) configured to receive the first signal through a first shadow buffer (211), the second signal through a second shadow buffer (221), the third signal through a third shadow buffer (231) and the fourth signal through a fourth shadow buffer (241), and a first glitch suppression buffer (115) coupled to a common node of an input of the first main buffer (111) and an input of the first shadow buffer (211).
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