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21.发明授权Integrated circuit, communication unit and method for improved amplitude resolution of an RF-DAC 有权用于RF-DAC的改善幅度分辨率的集成电路，通信单元和方法
公开(公告)号：EP2383893B1
公开(公告)日：2014-02-26
申请号：EP11003163.0
申请日：2011-04-14
CPC分类号： H03K7/08 , H03F3/2176 , H03M1/68 , H03M1/747 , H03M1/822 , H04B14/026
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22.发明公开
公开(公告)号：EP2658130A1
公开(公告)日：2013-10-30
申请号：EP12858683.1
申请日：2012-10-31
发明人： NAKAMOTO, Seiko , NAKANISHI, Junya
IPC分类号： H03M1/74
摘要： A digital-analog converter circuit includes sampling capacitive elements (111, 112, ..., 11N) of which one ends are to be electrically connected to and disconnected from input terminals (D1, D2, ..., DN), to which digital signals are input, via a switch unit (SWu10), an operational amplifier (501), a switch (301) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements (111, 112, ..., 11N) and an inverting input terminal of the operational amplifier (501), and a switch unit (SWu40) that is disposed between nodes between the switch unit (SWu10) and the sampling capacitive elements (111, 112, ..., 11N) and the output terminal of the operational amplifier (501) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch (301) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu40).
摘要翻译： 数模转换器电路包括对其一端电连接到输入端（D1，D2，...，DN）并与其断开的电容元件（111,112，...，11N）进行采样，其中 数字信号经由开关单元（SWu10），运算放大器（501），能够电连接和断开取样电容元件（111,112，...，11N）的另一端的开关（301）输入， 和运算放大器（501）的反相输入端子和设置在开关单元（SWu10）和采样电容元件（111,112，...，11N）之间的节点之间的开关单元（SWu40）和 运算放大器（501）的输出端子，并且能够连接和断开它们。 包括在开关（301）中的MOS晶体管的导通电阻值被设置为大于包括在开关单元（SWu40）中的MOS晶体管的导通电阻值。
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23.发明公开
公开(公告)号：EP2634922A2
公开(公告)日：2013-09-04
申请号：EP13156377.7
申请日：2013-02-22
发明人： Clara, Martin , Gruber, Daniel , Klatzer, Wolfgang
CPC分类号： H03M1/1061 , H03M1/742
摘要： Representative implementations of devices and techniques provide digital-to-analog conversion of signals while minimizing switching related errors. Digital to analog converter (DAC) cells may be arranged to include one or more operating states in addition to binary output states, and may employ a switching technique to "dump" the DAC cell between binary outputs. Further, an array of DAC cells may include a partial set of redundant DAC cells for implementation of the switching technique.
摘要翻译： 设备和技术的代表性实现提供信号的数模转换，同时最小化与开关相关的错误。 数模转换器（DAC）单元可以被布置成除了二进制输出状态之外还包括一个或多个操作状态，并且可以采用切换技术来在二进制输出之间“转储”DAC单元。 此外，DAC单元的阵列可以包括用于实现切换技术的部分冗余DAC单元组。
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24.发明公开Digital to analog converter with gradient error correction 有权Digital-Analog-Wandler mit Korrektur des Gradientsfehlers
公开(公告)号：EP2579463A1
公开(公告)日：2013-04-10
申请号：EP11183730.8
申请日：2011-10-03
IPC分类号： H03M1/10 , H03M1/00 , H03M1/06 , H03M1/20 , H03M1/68 , H03M1/74 , H03M1/66 , H03M3/02 , H03M3/04 , H03M7/00
CPC分类号： H03M1/1047 , H03M1/007 , H03M1/1042 , H03M1/661 , H03M1/68 , H03M1/685 , H03M1/687 , H03M1/745 , H03M1/747 , H03M7/3026 , H03M7/3028
摘要： A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate.
摘要翻译： 公开了一种数模转换器。 该转换器包括梯度校正模块，该梯度校正模块基于梯度误差的模型产生校正项。 然后将校正项应用于数字域中的信号路径或应用于模拟域中的数模转换器的输出。 用于产生校正项的模型基于当前源元素阵列中的垂直梯度误差，其可以使用二阶多项式来建模和校准。 此外，公开了具有奈奎斯特DAC和过采样DAC的数模转换器。 当使能过采样DAC时，可能会增加奈奎斯特DAC的分辨率，同时降低转换速率。
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25.发明公开Integrated circuit, communication unit and method for improved amplitude resolution of an RF-DAC 有权用于RF-DAC的改善幅度分辨率的集成电路，通信单元和方法
公开(公告)号：EP2383893A3
公开(公告)日：2013-01-23
申请号：EP11003163.0
申请日：2011-04-14
CPC分类号： H03K7/08 , H03F3/2176 , H03M1/68 , H03M1/747 , H03M1/822 , H04B14/026
摘要： An integrated circuit includes a digitally-controlled power generation stage (3324) for converting an input signal to a radio frequency carrier, the digitally-controlled power generation stage (3324) comprising a plurality of selectable switching devices capable of adjusting an envelope of the radio frequency carrier; and a pulse width modulator generator (1302, 1508) arranged to generate a pulse width modulator control signal and operably coupleable to the plurality of selectable switching devices of the digitally-controlled power generation stage (3324). The pulse width modulator generator (1302, 1508) inputs the pulse width modulator control signal to a subset of the plurality of the selectable switching devices such that a pulse width modulator signal adjusts the envelope radio frequency carrier output from the digitally-controlled power generation stage (3324).
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公开(公告)号：EP2541776A1
公开(公告)日：2013-01-02
申请号：EP11171905.0
申请日：2011-06-29
申请人： IMEC
发明人： Ingels, Mark
摘要： Described herein is a direct digital radio frequency modulator (1010) in which out of band quantisation noise is filtered directly at radio frequency. The modulator (1010) comprises a plurality of modulator elements (1012, 1014, 1016, 1018) each having a voltage bias transistor (1050). The transistor (1050) is tuned in accordance with finite impulse response filter coefficients. A pair of switches (EN0(1), RFin0, EN90(1), RFin90, EN180(1), RFin180, EN270(1), RFin270) is provided for each input phase. The RF signals are spaced apart from one another in accordance with a duty cycle related to the number of input phases.
摘要翻译： 这里描述的是直接数字射频调制器（1010），其中带外量化噪声直接在射频频率下被滤波。 调制器（1010）包括多个具有电压偏置晶体管（1050）的调制器元件（1012,1014,1016,1018）。 晶体管（1050）根据有限脉冲响应滤波器系数进行调谐。 为每个输入阶段提供一对开关（EN0（1），RFin0，EN90（1），RFin90，EN180（1），RFin180，EN270（1），RFin270）。 RF信号根据与输入相位数相关的占空比彼此间隔开。
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公开(公告)号：EP2226943A3
公开(公告)日：2012-11-14
申请号：EP10002305.0
申请日：2010-03-05
申请人： Yamaha Corporation
发明人： Yasui, Shoji
CPC分类号： H03M1/0845 , H03M1/808
摘要： There is provided a correction circuit for a D/A converter, comprising: a constant current source to be connected between high- and low-potential power source lines for supplying a power source voltage to the D/A converter; and a current controller which is adapted to control a current flowing to the constant current source in accordance with an input digital signal to the D/A converter, so as to reduce a variation of a sum of currents which, when the input digital signal to the D/A converter is changed, flows to the low-potential power source line from the high-potential power source line through the D/A converter and the constant current source, respectively.
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公开(公告)号：EP1685721B1
公开(公告)日：2012-07-25
申请号：EP04769596.0
申请日：2004-10-08
申请人： Nokia Corporation
CPC分类号： H04B1/04 , H03D7/1441 , H04B2001/0491
摘要： A digital to RF-conversion device that combines the D/A conversion function and the upconversion function by a RF-carrier or IF-signal. The device comprises a plurality of parallel unit cells, each of which is a mixer cell type converter having a differential data switch section connected in series to a differential LO-switch pair. The differential LO-switch is further connected in series to a current source. Each unit cell is adapted to receive a control voltage indicative of a data signal value.
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公开(公告)号：EP1810413A4
公开(公告)日：2009-12-09
申请号：EP04801280
申请日：2004-12-01
申请人： NOKIA CORP
CPC分类号： H03M1/745 , H03C3/40 , H03D7/1441 , H04B1/04 , H04B2001/0491 , H04L27/36
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公开(公告)号：EP2050192A1
公开(公告)日：2009-04-22
申请号：EP07792141.9
申请日：2007-08-01
发明人： ZEBEDEE, Patrick
IPC分类号： H03M1/74
CPC分类号： H03M1/0607 , H03M1/804
摘要： A digital/analogue converter for converting an input n-bit digital code (n >1), comprising: a switched capacitor digital/analogue converter (14) having a plurality of capacitors (C1...Cn). The lower plate of each is connectable, dependent on the input digital code, to either a first reference voltage (V2) or a second reference voltage (V3) different from the first reference voltage. The converter also comprises at least one further capacitor (CP), and a switching arrangement (18,19) for connecting the lower plate of the or each first further capacitor to either a third reference voltage or a fourth reference voltage different from the third reference voltage. The input to the first switching arrangement is independent of the input digital code. In the decoding phase, the output voltage floats to a voltage that depends on both the input data code and the direction and magnitude of charge injection across the further capacitor(s) (CP).
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