公开(公告)号：EP1540828A1

公开(公告)日：2005-06-15

申请号：EP03795107.6

申请日：2003-08-06

申请人： Koninklijke Philips Electronics N.V.

发明人： PESSOLANO, Francesco ,  VAN DIJK, Victor, E., S.

IPC分类号： H03M5/02

CPC分类号： H04L25/0266 ,  G01R31/318538 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a method for coding information in an electronic circuit and an electronic circuit for coding information, said circuit comprising at least two electrically coupled signal paths (X0, X1). The invention is based on the idea that cross-talk between two electrically coupled signal paths (X0, X1) can be utilized to perform logical computation. A signal is propagating on two signal paths (X0, X1) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X0, X1) determines the logic value of the output signal (X) to be produced. If the signal on the first path (X0) propagates faster than the signal on the second path (X1), an output signal (X) having a first logic value is produced. If the signal on the second path (X1) propagates faster than the signal on the first path (X0), an output signal (X) having a second logic value is produced.

公开(公告)号：EP0584265A4

公开(公告)日：1994-05-18

申请号：EP92913146

申请日：1992-05-15

申请人： THESEUS RESEARCH INC

发明人： FANT KARL M ,  BRANDT SCOTT A

IPC分类号： G06F7/00 ,  G06F7/50 ,  G06F7/505 ,  G06F11/08 ,  H03K19/08 ,  H03K19/096 ,  H03K19/23 ,  H03M5/02 ,  H03M5/16 ,  G06F1/00

CPC分类号： G06F7/502 ,  G06F7/00 ,  G06F7/5052 ,  G06F11/085 ,  G06F2207/4822 ,  H03K19/0813 ,  H03K19/096 ,  H03K19/23 ,  H03M5/02 ,  H03M5/16

摘要： An information processing system comprising at least one information processing unit (A, B). The information processing unit has at least one information processing member which resolves allowed values. Allowed values include at least one data value and at least one non-data value. At least one non-data value is a null value. The system further comprises a plurality of information transmission elements (OA, NA) for transmitting values to and from the information processing unit (A) and the information processing member.

公开(公告)号：EP0346776A1

公开(公告)日：1989-12-20

申请号：EP89110495.2

申请日：1989-06-09

申请人： EASTMAN KODAK COMPANY

发明人： Wash, Michael Lee c/o EASTMAN KODAK COMPANY

IPC分类号： G11B20/14 ,  H03M5/02

CPC分类号： H03M5/12

摘要： Electrical circuit suitable for decoding a binary data stream that has been encoded in a sequential bitcell code format, the encoding resulting in an encoded signal waveform that carries clock information and data information, which electrical circuit comprises: a) a separator means (i) for inputting the encoded signal waveform and separating the clock information from the data information, and (ii) for generating an output clock signal and an output data signal, for each of a succession of bitcells; b) a clock signal integrator for calculating the duration of the bit cell; c) a circuit integrator for determining the center of the bitcell; d) a comparer means for: (i) determining in which part of the bitcell is the data signal, (ii) assigning the decoded signal a first valuation if the data signal is in the first part of the bitcell, and a second valuation if the data signal is in the second part of the bitcell. This circuit preserves the self clocking, velocity insensitive features of the code format.

摘要翻译： 电路，适用于对已经以顺序位单元代码格式编码的二进制数据流进行解码，该编码产生承载时钟信息和数据信息的编码信号波形，该电路包括：a）分离器装置（i），用于 输入编码信号波形并从数据信息中分离出时钟信息，以及（ii）为每个比特单元产生一个输出时钟信号和一个输出数据信号; b）用于计算位单​​元的持续时间的时钟信号积分器; c）用于确定位单元的中心的电路积分器; d）比较器装置，用于：（i）确定所述位单元的哪一部分是所述数据信号，（ii）如果所述数据信号位于所述位单元的所述第一部分中，则将所述解码信号分配给第一估值，以及如果 数据信号位于位单元的第二部分。 该电路保留自定时，速度不敏感的代码格式特征。

公开(公告)号：EP0155455A1

公开(公告)日：1985-09-25

申请号：EP85100614.8

申请日：1985-01-22

申请人： ANT Nachrichtentechnik GmbH

发明人： Bredemeier-Klonki, Volker, Dipl.-Ing. ,  Annecke, Karl-Heinz, Dr. Ing.

IPC分类号： H04L25/49 ,  H03M5/02

CPC分类号： H04L25/4908

摘要： Die Erfindung betrifft ein Verfahren und eine Schaltungsanordnung zur Durchführung desselben zum Umsetzen eines digitalen Eingangssignales aus einem 5-Bit-Codewort in ein 6-Bit-Codewort mit positivem und negativem Modus und ist dadurch gekennzeichnet, daß etwa gleichzeitig mit oder während der Codierung des laufenden entsprechend der Vorgabe des augenblicklich vorliegenden Modus zu codierenden 5-Bit-Codewortes des Eingangssignals der Modus für das folgende zu codierende 5-Bit-Codewort des Eingangssignal bestimmt wird (Figur 2). Das Verfahren gestattet damit den Einsatz von solchermaßen realisierten Schaltungsanordnungen bei sehr viel höheren Betriebsfrequenzen (etwa Faktor 2).

摘要翻译： 用于编码数字输入信号的电路装置，其根据第一二进制码被编码的五位代码字根据具有正和负的第二二进制码被转换成六位代码字 负模式，其中在当前五位代码的评估（C）期间，在模式选择计算机（MR）中确定输入信号的要编码的下一个五位代码字（下一个模式，FM）的模式 字，根据瞬时当前模式的导入被编码，并且其中根据下表进行转换：五位六位模式+下一模式模式下一模式0 00000 50 110010 + 50 110010 - 1 00001 51 110011 - 33 100001 + 2 00010 54 110110 - 34 100010 + 3 00011 35 100011 + 35 100011 - 4 00100 53 110101 - 36 100100 + 5 00101 37 100101 + 37 100101 - 6 00110 38 100110 + 38 100110 - 7 00111 39 100111 - 7 000111 - 8 01000 43 101011 - 40 101000 + 9 01001 41 101001 + 41 101001 - 1 0 01010 42 101010 + 42 101010 - 11 01011 11 001011 + 11 001011 - 12 01100 44 101100 + 44 101100 - 13 01101 45 101101 - 5 000101 + 14 01110 46 101110 - 6 000110 + 15 01111 14 001110 + 14 001110 - 16 10000 49 110001 + 49 110001 - 17 10001 57 111001 - 17 010001 + 18 10010 58 111010 - 18 010010 + 19 10011 19 010011 + 19 010011 - 20 10100 52 110100 + 52 110100 - 21 10101 21 010101 + 21 010101 - 22 10110 22 010110 + 22 010110 - 23 10111 23 010111 - 20 010100 + 24 11000 56 111000 + 24 011000 + 25 11001 25 011001 + 25 011001 - 26 11010 26 011010 + 26 011010 - 27 11011 27 011011 - 10 001010 + 28 11100 28 011100 + 28 011100 - 29 11101 29 011101 - 9 001001 + 30 11110 30 011110 - 12 001100 + 31 11111 13 001101 + 13 001101 - ABCDE ABCDEF ABCDEF，其中五位代码的最后四位位置（B，C，D，E） 在模式选择计算机（MR）中检查字用于确定下一模式（FM），其中通过在瞬时模式的情况下反转瞬时模式来产生下一模式 这些位位中的奇数个二进制位，并且瞬时模式被保留为码字11和20的下一个模式（FM），对于具有瞬时负方式的码字7和具有瞬时正值的码字24 在这些比特位置（B，C，D，E）中偶数个二进制位的情况下，模式选择计算机（MR）的特征在于，提供了异或成员（EXOR 1） 其四个输入由五位代码字的最后四位（B，C，D，E）起作用，其输出被传送到AND成员（UND）的一个输入，该 提供了第二个异或成员（EXOR 2），其一个输入端与AND部件的输出端连接，另一个输入端通过瞬时模式进行操作，并采用二进制信号“ 0“或”1“，提供了一个解码电路（Dec），其输入作用 通过五位代码字的位（A，B，C，D，E）和瞬时模式进行编程，其输出（Y）为代码字11和20产生二进制零，为 具有瞬时负模式的代码字7和具有瞬时正模式的代码字24并且与AND成员的另一个输入连接，并且下一个模式（FM）的二进制信号可以在 第二个独家OR成员（EXOR 2）。

公开(公告)号：EP4198753B1

公开(公告)日：2024-09-25

申请号：EP21306804.2

申请日：2021-12-16

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/20 ,  H03M5/02 ,  G11C7/10 ,  H04L25/02 ,  H04L1/00 ,  H04L69/22

CPC分类号： G06F13/4291 ,  G06F13/4072 ,  G06F13/4077 ,  G06F13/4068 ,  H03M5/02 ,  H04L69/22 ,  G06F13/20 ,  H04L1/0083 ,  H04L25/0264

公开(公告)号：EP4198755A1

公开(公告)日：2023-06-21

申请号：EP22305752.2

申请日：2022-05-20

申请人： STMicroelectronics (Research & Development) Limited

发明人： APARCIO, Sergio Miguez ,  SARACHI, Benjamin Thomas

IPC分类号： G06F13/40 ,  G06F13/42 ,  H04L25/02 ,  G11C7/10 ,  H03M5/02 ,  H04L69/22 ,  G06F13/20 ,  H04L1/00 ,  H04L47/36

摘要： The present disclosure relates to a system comprising: a serial bus having a data wire and a clock wire; a primary device connected to the bus and configured to provide a clock signal on the clock wire and to provide control bits on the serial bus; and one or a plurality of secondary devices each connected to the bus, a format of each frame (F2) transmitted on the serial bus is determined by a number (N, P, Q) of control bits (ctrl) at at least one location (L2, L3, L4) of said frame.

公开(公告)号：EP4198753A1

公开(公告)日：2023-06-21

申请号：EP21306804.2

申请日：2021-12-16

申请人： STMicroelectronics (Research & Development) Limited

发明人： RAYNOR, Jeff M. ,  APARICIO, Sergio Miguez ,  SARACHI, Benjamin Thomas

IPC分类号： G06F13/40 ,  G06F13/42 ,  H04L25/02 ,  G11C7/10 ,  H03M5/02

摘要： The present disclosure relates to a secondary device (S) comprising a first port (S1) receiving a clock signal from a first port (M1) of a primary device (M) and a second port (S2) connected to a second port (M2) of the primary device (M). The clock signal (ZPclk) determines, for each bit transmission (DATA, ACK, CTRL), first, second, third and fourth successive phases. The secondary device (S) puts its second port (S2) in a high impedance state during the first, second and fourth phases of each bit transmission. During the third phase of each transmission of a bit of data from the secondary device (S) to the primary device (M), the secondary device (S) discharges its second port (S2) when the transmitted bit has a first value and leaves its second port (S2) in a high impedance state when the transmitted bit has a second value.

公开(公告)号：EP3286910A1

公开(公告)日：2018-02-28

申请号：EP16783934

申请日：2016-04-22

申请人： SCOTT TECH INC

发明人： CHROSTOWSKI ANDREW

IPC分类号： H04N5/33 ,  A61B5/00 ,  G08B21/02 ,  H03M5/02

CPC分类号： H04N5/33 ,  A61B5/0022 ,  A61B5/0024 ,  A61B5/0059 ,  A61B5/01 ,  A61B5/02055 ,  A61B5/1123 ,  A61B5/117 ,  A61B5/6803 ,  A61B5/6804 ,  A61B5/6823 ,  A61B5/742 ,  A61B5/747 ,  A61B2503/20 ,  A61B2560/0242 ,  G01J5/025 ,  G01J2005/0077 ,  G08B21/0415 ,  G08B21/0453 ,  G08B21/0476 ,  G08B25/016 ,  G08B27/001 ,  H04N5/2256

摘要： A portable signaling device includes an infrared (IR) emitter held by housing that emits pulses of IR radiation. Processors are operably connected to the IR emitter and sensors monitor the operations of the wearer which receive data parameters from the sensors allowing the processors to generate a status message based on the data parameters that are received. This status message represents the operating status of the wearer, which the IR emitter transmits by emitting pulse sequences of IR radiation that are configured to be received by an IR detector.

公开(公告)号：EP3276835A1

公开(公告)日：2018-01-31

申请号：EP15887841.3

申请日：2015-04-21

申请人： IDAC Holdings, Inc.

发明人： CHUNG, Hae ,  CHUNG, Han

IPC分类号： H03M5/02 ,  H04L1/00

CPC分类号： H04L25/4917 ,  H03M5/02 ,  H03M5/20 ,  H03M7/30 ,  H04L1/00 ,  H04L27/04 ,  H04L27/365 ,  H04L27/366

摘要： Disclosed are a real number M-ary signal encoding method, where M is a real number having N time dimensions and L frequency dimensions, and an encoding apparatus using the encoding method. The real number M-ary encoding apparatus according to the present invention comprises a coding unit which codes every K (K is an integer) binary bit units of binary data DATA to generate a first input code and a second input code, a first signal generator which receives the first input code and generates N 1 number of M 1 -ary signals, a second signal generator which receives the second input code and generates N 2 number of M 2 -ary signals, and a first time division multiplexing module which temporally multiplexes the N 1 number of M 1 -ary signals and the N 2 number of M 2 -ary signals to generate a real number M-ary signal which utilizes a voltage ratio a (a=A 2 /A 1 ) used for M 1 -ary and M 2 -ary signals to minimize a transmission error rate.

摘要翻译： 公开了一种实数M进制信号编码方法，其中M是具有N个时间维度和L个频率维度的实数，以及使用该编码方法的编码装置。 根据本发明的实数M进制编码设备包括编码单元，该编码单元对二进制数据DATA的每个K（K是整数）二进制位单元进行编码以生成第一输入码和第二输入码，第一信号生成器 其接收第一输入码并生成N1个M1元信号;第二信号发生器，其接收第二输入码并生成N2个M2元信号;以及第一时分多路复用模块，其在时间上多路复用N1个 M1-ary信号和M2-ary信号的N2个数生成实数M-ary信号，其利用用于M1-ary和M2-ary信号的电压比a（a = A2 / A1）以使传输误差最小化 率。

公开(公告)号：EP3075117A1

公开(公告)日：2016-10-05

申请号：EP14821340.8

申请日：2014-11-21

申请人： Qualcomm Incorporated

发明人： HOLLIS, Timothy Mowry

IPC分类号： H04L25/49 ,  G06F13/38 ,  H03M5/02

CPC分类号： H04L25/4917 ,  G06F13/38 ,  H03M5/02 ,  H04L25/4915

摘要： System, methods and apparatus are described that reduce the power consumed by a multi-level encoded communications link. In one example, different logic states of a 4-level pulse amplitude modulation encoded transmission consume greater power than other logic states. The fraction of primary bits in a first logic state in multi-bit data symbols may determine whether the primary bits are inverted prior to transmission. The fraction of secondary bits in the first logic state in the multi-bit data symbols may determine whether the secondary bits are inverted prior to transmission. The primary bits may be swapped with the secondary bits is more secondary bits are in the first logic state than primary bits in the first logic state.