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40 条记录 (耗时 0.017 秒)

    Semiconductor integrated circuit device for supplying a bias current to DA converters
    36.
    发明公开
    Semiconductor integrated circuit device for supplying a bias current to DA converters 失效
    HalbleiterintegriertesSchaltungsgerätzur Versorgung eines Bias-StromsfürDigital-Analogwandler。

    公开(公告)号：EP0458659A2

    公开(公告)日：1991-11-27

    申请号：EP91400494.0

    申请日：1991-02-22

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Gotoh, Kunihiko ,  Sekido, Yuuji

    IPC分类号： H03M1/06 ,  G05F3/28 ,  H03M1/66 ,  G05F1/00

    CPC分类号： H03M1/0604 ,  G05F3/262 ,  H03M1/662 ,  H03M1/742

    摘要： A semiconductor integrated circuit device comprising a bias generating circuit having an operational amplifier connected to receive an input voltage at its inverting input terminal to produce a gate voltage, a field effect transistor having its gate connected to receive the gate voltage from said operational amplifier and its drain connected to a resistor and to a noniverting input terminal of said operational amplifier, and further field effect transistor having its gate connected to receive the gate voltage from said operational amplifier to produce a current corresponding to the input voltage, one group of current sources responsive to an output voltage of said bias generating circuit to produce a plurality of currents of an equal magnitude and one switching circuit responsive to an input digital value to selectively output the currents from said group of current sources to its common output.

    摘要翻译： 一种半导体集成电路器件，包括偏置产生电路，该偏置产生电路具有连接以在其反相输入端接收输入电压以产生栅极电压的运算放大器;场效应晶体管，其栅极连接以接收来自所述运算放大器的栅极电压， 漏极连接到所述运算放大器的电阻器和非输入输入端子，以及另外的场效应晶体管，其栅极连接以接收来自所述运算放大器的栅极电压，以产生对应于输入电压的电流，一组电流源响应 到所述偏置产生电路的输出电压，以响应于输入数字值产生相等幅度的多个电流和一个开关电路，以选择性地将来自所述一组电流源的电流输出到其公共输出。

    Input/output protection circuit and semiconductor device having the same
    37.
    发明公开
    Input/output protection circuit and semiconductor device having the same 失效
    输入/输出保护电路和具有相同功能的半导体器件

    公开(公告)号：EP0454091A3

    公开(公告)日：1991-11-27

    申请号：EP91106606.6

    申请日：1991-04-24

    申请人： FUJITSU LIMITED

    发明人： Mizutani, Toru ,  Kobayashi, Osamu ,  Gotoh, Kunihiko

    IPC分类号： H03F1/52 ,  H01L27/02 ,  H03G11/00

    CPC分类号： H03F1/523

    摘要： A protection circuit includes a first protection circuit (13), which is coupled between a signal output terminal (OT) of an internal circuit and an external connection terminal (11) and which prevents an abnormal voltage applied to the external connection terminal from being input to the signal output terminal. The protection circuit also includes a second protection circuit (14), which is coupled between a signal input terminal (IN(-)) of the internal circuit and the external connection terminal and which prevents the abnormal voltage applied to the external connection terminal from being input to the signal input terminal. The signal input terminal is operatively coupled to the signal output terminal via the first and second protection circuit and has an impedance higher than that of the signal output terminal.

    Differential amplifier circuit improved to shorten a circuit recovery time thereof
    39.
    发明公开
    Differential amplifier circuit improved to shorten a circuit recovery time thereof 失效
    改善放大电路恢复时间的差分放大器电路

    公开(公告)号：EP0254323A3

    公开(公告)日：1989-02-15

    申请号：EP87110760.3

    申请日：1987-07-24

    申请人： FUJITSU LIMITED

    发明人： Kobayashi, Osamu ,  Gotoh, Kunihiko

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45076

    摘要： A differential amplifier circuit whereby a recovery time produced due to large amplitude of a voltage difference appearing between differential input signals (Sl, S2) fed to a differential input stage of the differential amplifier circuit is shortened by adding two transistors (Tlʹ, T2ʹ) to an ordinary differential amplifier circuit (Tl, T2) so that the two transistors (Tlʹ, T2ʹ) are connected with nodes (Nl, N2) at which two transistors (Tl, T2) of the differential input stage are connected with two loads (T3, T4) of the differential input stage, respectively. the one (Tlʹ) of the two added transistors (Tlʹ, T2ʹ) directly contributes to shorten the recovery time by reducing a voltage at one of the nodes (N2) from which an output signal voltage of the differential amplifier circuit is obtained, and the other (T2ʹ) of the two added transistors is for obtaining symmetric property of the differential amplifier circuit.

    Comparator circuit having improved output characteristics
    40.
    发明公开
    Comparator circuit having improved output characteristics 失效
    比较器电路具有改进的输出特性。

    公开(公告)号：EP0193901A2

    公开(公告)日：1986-09-10

    申请号：EP86102660.7

    申请日：1986-02-28

    申请人： FUJITSU LIMITED

    发明人： Kousaka, Kunimitsu ,  Gotoh, Kunihiko ,  Kobayashi, Osamu

    IPC分类号： H03K5/24

    CPC分类号： H03K5/2481

    摘要： In a comparator circuit comprising a first power supply terminal means and a second power supply terminal means, a differential stage connected between the first power supply terminal means and the second power supply terminal means, a first input signal having a reference level and a second input signal having a level which is compared with the reference level being input to each of a pair of input terminals of the differential stage, respectively, an output signal having a level which is determined in accordance with the level of the second input signal being output from an output terminal of the differential stage, and an output stage connected to the output terminal of the differential stage, through which output stage the output signal of the differential stage is amplified; a bypass circuit through which a predetermined constant current flows is connected between the output terminal of the differential stage and the second power supply terminal means.
    The bypass circuit may be always closed or may be closed only when the output level of the output stage has reached the predetermined value.