公开(公告)号：EP3087588A1

公开(公告)日：2016-11-02

申请号：EP13900562.3

申请日：2013-12-27

申请人： Intel Corporation

发明人： SUNG, Seung Hoon ,  TURKOT, Robert, B., Jr. ,  MURTHY, Anand ,  KIM, Seiyon ,  KUHN, Kelin

IPC分类号： H01L21/3065 ,  H01L21/336

CPC分类号： H01L29/6681 ,  H01L21/3065 ,  H01L21/67069 ,  H01L29/0673 ,  H01L29/42392

摘要： The present disclosure relates to a method of etching sacrificial material. The method includes supplying a semiconductor substrate in a reaction chamber, wherein the substrate includes a channel disposed on the substrate and a sacrificial layer disposed on at least a portion of the channel. The method further includes supplying an interhalogen vapor to the reaction chamber, etching at least a portion of the sacrificial layer with the interhalogen vapor and exposing at least a portion of said channel from under the sacrificial layer.

摘要翻译： 本公开涉及蚀刻牺牲材料的方法。 该方法包括在反应室中提供半导体衬底，其中衬底包括设置在衬底上的沟道和设置在通道的至少一部分上的牺牲层。 该方法还包括向反应室供应间卤素蒸气，用卤素蒸气蚀刻牺牲层的至少一部分，并从牺牲层下方暴露出所述通道的至少一部分。

公开(公告)号：EP1825501A2

公开(公告)日：2007-08-29

申请号：EP05854575.7

申请日：2005-12-15

申请人： Intel Corporation

发明人： HATTENDORF, Michael ,  HWANG, Jack ,  MURTHY, Anand ,  WESTMEYER, Andrew

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66628 ,  H01L21/26506 ,  H01L29/7834 ,  H01L29/7842

摘要： Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

公开(公告)号：EP1451864A2

公开(公告)日：2004-09-01

申请号：EP02791402.7

申请日：2002-12-10

申请人： INTEL CORPORATION

发明人： BOHR, Mark ,  AHMED, Shahriar ,  CHAMBERS, Stephen ,  GREEN, Richard ,  MURTHY, Anand

IPC分类号： H01L21/331

CPC分类号： H01L29/66287

摘要： The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate (112). Thereafter, a spacer (136) is formed at the topology. A base layer (140) is formed from epitaxial silicon above the spacer (136) and at the topology. A leakage block (158) is formed in the substrate by out-diffusion from the spacer (136). Thereafter a BJT is completed with the base layer (140) and the spacer (136).

公开(公告)号：EP1428263A2

公开(公告)日：2004-06-16

申请号：EP03764362.4

申请日：2003-07-03

申请人： INTEL CORPORATION

发明人： MURTHY, Anand ,  DOYLE, Brian ,  KAVALIEROS, Jack ,  CHAU, Robert

IPC分类号： H01L29/786

CPC分类号： H01L29/41733 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618

摘要： The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.