公开(公告)号：EP4202977A1

公开(公告)日：2023-06-28

申请号：EP22214363.8

申请日：2022-12-16

申请人： INTEL Corporation

发明人： NANDI, Debaleena ,  DEWEY, Gilbert ,  GHANI, Tahir ,  HARATIPOUR, Nazila ,  KOBRINSKY, Mauro J. ,  MURTHY, Anand

IPC分类号： H01L21/285 ,  H01L29/45 ,  H01L21/768

摘要： The formation of titanium contacts to silicon germanium (SiGe) comprises the formation of a titanium silicide layer in which the silicon for the titanium silicide layer is provided by flowing silane (disilane, trisilane, etc.) over a titanium layer at an elevated temperature. The titanium silicide layer can help limit the amount of titanium and germanium interdiffusion that can occur across the titanium silicide-silicon germanium interface, which can reduce (or eliminate) the formation of voids in the SiGe layer during subsequent anneal and other high-temperature processes. The surface of the SiGe layer upon which the titanium layer is formed can also be preamorphized via boron and germanium implantation to further improve the robustness of the SiGe layer against microvoid development. The resulting titanium contacts are thermally stable in that their resistance remains substantially unchanged after being subjected to downstream annealing and high-temperature processing processes.

公开(公告)号：EP3624200A1

公开(公告)日：2020-03-18

申请号：EP19183091.8

申请日：2019-06-28

申请人： INTEL Corporation

发明人： GLASS, Glenn ,  MURTHY, Anand ,  BOMBERGER, Cory ,  GHANI, Tahir ,  KAVALIEROS, Jack ,  CHOUKSEY, Siddarth ,  SUNG, Seung Hoon ,  GUHA, Biswajeet ,  AGRAWAL, Ashish

IPC分类号： H01L29/06 ,  H01L27/092 ,  H01L29/775 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/165 ,  H01L29/78

摘要： A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.

公开(公告)号：EP3087588B1

公开(公告)日：2019-03-20

申请号：EP13900562.3

申请日：2013-12-27

申请人： Intel Corporation

发明人： SUNG, Seung Hoon ,  TURKOT, Robert B. Jr. ,  MURTHY, Anand ,  KIM, Seiyon ,  KUHN, Kelin

IPC分类号： H01L21/3065 ,  H01L21/336 ,  H01L29/423 ,  H01L21/67 ,  H01L29/66 ,  H01L29/06

公开(公告)号：EP2356670A2

公开(公告)日：2011-08-17

申请号：EP09832392.6

申请日：2009-12-02

申请人： Intel Corporation

发明人： SIMONELLI, Danielle ,  MURTHY, Anand

IPC分类号： H01L21/20 ,  H01L21/336

CPC分类号： H01L21/0245 ,  H01L21/02381 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

摘要： Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.

公开(公告)号：EP4345894A1

公开(公告)日：2024-04-03

申请号：EP23187397.7

申请日：2023-07-25

申请人： INTEL Corporation

发明人： SHARMA, Abhishek ,  Ghani, Tahir ,  MURTHY, Anand ,  Gomes, Wilfred ,  Suthram, Sagar ,  Ranade, Pushkar

IPC分类号： H01L23/522

摘要： An integrated circuit (IC) die includes a plurality of front-side metallization layers including a first front-side metallization layer and one or more additional front-side metallization layers, a plurality of back-side metallization layers formed on the plurality front side metallization layers including a first back-side metallization layer and one or more additional back-side metallization layers, wherein the first front-side metallization layer is proximate to the first back-side metallization layer, and a vertical metallization structure formed through at least the first front-side metallization layer and the first back-side metallization layer, wherein the vertical metallization structure electrically connects a first metallization structure on one of the one or more additional front-side metallization layers to a second metallization structure on one of the one or more additional back-side metallization layers. Other embodiments are disclosed and claimed.

公开(公告)号：EP4203059A1

公开(公告)日：2023-06-28

申请号：EP22203503.2

申请日：2022-10-25

申请人： INTEL Corporation

发明人： SHAH, Rushabh ,  GLASS, Glenn ,  HASAN, Mohammad ,  MURTHY, Anand ,  BOMBERGER, Cory

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  B82Y10/00

摘要： Cap layers (144) are formed on silicon germanium (SiGe) source/drain regions (140) of field-effect transistors, in particular FinFETs and GAA-FETs, to provide etch resistance to processing steps that can occur in a semiconductor manufacturing process between formation of the SiGe source/drain regions and metal contact (152) formation. The cap layers (144) comprise boron and are thin (e.g., 2 nm or less) to provide for a low metal contact resistance. The atomic concentration of boron in the cap layer is in a range of about 0.2-20%, and the cap layer preferably further comprises Si and Ge. In addition to providing etch resistance, the cap layer provides for a thermally stable contact resistance as the cap layer can prevent or limit the creation of voids in the SiGe layer by preventing or limiting the diffusion of germanium from the SiGe layer into the metal (148, 152) in subsequent annealing and other high-temperature processing steps.As metal-silicon-germanium region (168) is preferably formed between the source/drain region (140) and the metal contact (152).

公开(公告)号：EP4181211A1

公开(公告)日：2023-05-17

申请号：EP22200110.9

申请日：2022-10-06

申请人： INTEL Corporation

发明人： AGRAWAL, Ashish ,  MURTHY, Anand ,  KAVALIEROS, Jack ,  PAUL, Rajat ,  DEWEY, Gilbert ,  SUNG, Seung Hoon ,  GHOSE, Susmita

IPC分类号： H01L29/775 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L21/324 ,  B82Y10/00 ,  H01L29/165

摘要： Techniques are provided herein to form semiconductor devices having strained channel regions. In an example, semiconductor nanoribbons of silicon germanium (SiGe) or germanium tin (GeSn) may be formed and subsequently annealed to drive the germanium or tin inwards along a portion of the semiconductor nanoribbons thus increasing the germanium or tin concentration through a central portion along the lengths of the one or more nanoribbons. Specifically, a nanoribbon may have a first region at one end of the nanoribbon having a first germanium concentration, a second region at the other end of the nanoribbon having substantially the same first germanium concentration (e.g., within 5%), and a third region between the first and second regions having a second germanium concentration higher than the first concentration. A similar material gradient may also be created using tin. The change in material composition (gradient) along the nanoribbon length imparts a compressive strain.

公开(公告)号：EP4181208A1

公开(公告)日：2023-05-17

申请号：EP22200636.3

申请日：2022-10-10

申请人： INTEL Corporation

发明人： AGRAWAL, Ashish ,  MURTHY, Anand ,  KAVALIEROS, Jack T. ,  PAUL, Rajat K. ,  DEWEY, Gilbert ,  GHOSE, Susmita ,  SUNG, Seung Hoon

IPC分类号： H01L29/06 ,  H01L21/336 ,  H01L29/775 ,  H01L29/423 ,  H01L21/324 ,  H01L29/165 ,  H01L29/10 ,  B82Y10/00

摘要： Techniques are provided herein to form semiconductor devices having nanowires with an increased strain. A thin layer of silicon germanium or germanium tin can be deposited over one or more suspended nanoribbons. An anneal process may then be used to drive the silicon germanium or germanium tin throughout the one or more semiconductor nanoribbons, thus forming one or more nanoribbons with a changing material composition along the lengths of the one or more nanoribbons. In some examples, at least one of the one or more nanoribbons includes a first region at one end of the nanoribbon having substantially no germanium, a second region at the other end of the nanoribbon having substantially no germanium, and a third region between the first and second regions having a substantially uniform non-zero germanium concentration. The change in material composition along the length of the nanoribbon imparts a compressive strain.

公开(公告)号：EP4109557A1

公开(公告)日：2022-12-28

申请号：EP22179997.6

申请日：2022-06-20

申请人： INTEL Corporation

发明人： MEHANDRU, Rishabh ,  CEA, Stephen ,  GHANI, Tahir ,  KEYS, Patrick ,  LILAK, Aaron D. ,  MURTHY, Anand ,  WEBER, Cory

IPC分类号： H01L29/775 ,  H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/165 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  B82Y10/00

摘要： Integrated circuitry comprising transistor structures with a source/drain etch stop layer to limit the depth of source and drain material relative to a channel of the transistor. A portion of a channel material layer may be etched in preparation for source and drain materials. The etch may be stopped at an etch stop layer buried between a channel material layer and an underlying planar substrate layer. The etch stop layer may have a different composition than the channel layer while retaining crystallinity of the channel layer. The source and drain etch stop layer may provide adequate etch selectivity to ensure a source and drain etch process does not punch through the etch stop layer. Following the etch process, source and drain materials may be formed, for example with an epitaxial growth process. The source and drain etch stop layer may be, for example, primarily silicon and carbon.

公开(公告)号：EP4300591A1

公开(公告)日：2024-01-03

申请号：EP23173199.3

申请日：2023-05-12

申请人： INTEL Corporation

发明人： NANDI, Debaleena ,  ZIGONEANU, Imola ,  DEWEY, Gilbert ,  JAHAGIRDAR, Anant H. ,  KENNEL, Harold W. ,  PATEL, Pratik ,  MURTHY, Anand ,  CHOI, Chi-Hing ,  KOBRINSKY, Mauro J. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66

摘要： Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm 2 .