公开(公告)号：EP0552979A2

公开(公告)日：1993-07-28

申请号：EP93300475.6

申请日：1993-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han, Hong Soo

IPC: H03M13/22 ,  H04N7/00

CPC classification number: H03M13/2764 ,  H04N5/602 ,  H04N7/083

Abstract: First and second memory means (4,5) are used as buffers during de-interleaving of data. Interleaved data is written into one memory means (4,5) while data is read from the other memory means (4,5) in a de-interleaving manner. A write address generating means (1) generates addresses for storing input interleaved data. A read address generating means (6) generates addresses for reading out data from the memory means (4,5) in a de-interleaved manner. De-interleaving is achieved by applying the read address signals to the memory means (4,5) left shifted by three places relative to the write address signals. A selector means (8) is provided to selectively apply the write address signals and the read address signals to the memory means (4,5).

Abstract translation: 第一和第二存储器装置（4,5）在解交织数据期间用作缓冲器。 交错数据被写入一个存储器装置（4,5），同时以解交织的方式从其他存储装置（4,5）读取数据。 写地址生成装置（1）产生用于存储输入交错数据的地址。 读取地址生成装置（6）产生用于以解交织的方式从存储装置（4,5）读出数据的地址。 通过将读取的地址信号相对于写入地址信号向左移位三位置的存储装置（4,5）来实现解交织。 提供选择器装置（8）以选择性地将写地址信号和读地址信号施加到存储装置（4,5）。

公开(公告)号：EP0551973A2

公开(公告)日：1993-07-21

申请号：EP93250005.1

申请日：1993-01-07

Applicant: E-SYSTEMS INC. ,  AMPEX SYSTEMS CORPORATION

Inventor： Rhines, Don S. ,  Handley, Kirk H. ,  McCoy, William D.

IPC: H03M13/22 ,  H03M13/00 ,  G11B20/18

CPC classification number: H03M13/2764 ,  G11B20/1866 ,  H03M13/2703 ,  H03M13/29 ,  H03M13/31

Abstract: The detection and correction of errors in digital data transmitted by or stored in a media channel is provided by processing the data through a triple orthogonally interleaved error correction system. On the transmit/store side of the system, the data is encoded three times prior to placement in the media channel with two different interleaving steps performed between the encoding steps. The first interleave is an orthogonal row shuffling interleave that provides enhanced protection against burst errors. On the receive/play back side, the data is decoded and deinterleaved, with included errors detected and corrected to enable recovery of the original data. To enhance the error correction, a circuit is used for generating a symbol accurate error flag identifying symbols containing errors thereby allowing the error correcting decoders to focus on and correct the data.

Abstract translation: 通过三维正交交织的纠错系统处理数据来提供由媒体信道发送或存储的数字数据中的错误的检测和校正。 在系统的发送/存储侧，数据在被放置在媒体信道之前被三次编码，在编码步骤之间执行两个不同的交织步骤。 第一交错是正交行混洗交错，其提供针对突发错误的增强的保护。 在接收/播放方面，数据被解码和解交织，检测和纠正了包含的错误，以恢复原始数据。 为了增强纠错，电路用于产生识别含有误差的符号的符号精确误差标志，从而允许纠错解码器聚焦并校正数据。

公开(公告)号：EP2182664B1

公开(公告)日：2018-09-12

申请号：EP09174486.2

申请日：2009-10-29

Applicant: Industrial Technology Research Institute

Inventor： Tsai, Chia-Lung ,  Hsieh, Yu-Tao ,  Hsu, Jen-Yuan ,  Ting, Pang-An

IPC: H04L1/00 ,  H03M13/27

CPC classification number: H04L1/0071 ,  H03M13/275 ,  H03M13/2764 ,  H03M13/6544 ,  H04L1/0065 ,  H04L1/04

Abstract: A wireless communication method implemented in a communication system includes receiving a first data sequence, and processing the first data sequence to obtain information containing at least one of a first number and a sampling spacing associated with the first data sequence. The method also includes permuting the first data sequence to generate a permuted second data sequence. Permuting the first data sequence includes determining a first parameter based on at least one of the first number and the sampling spacing, determining a second parameter based on at least one of the first parameter, the first number, and the sampling spacing, and determining a mapping relationship between a j-th data item of the permuted second data sequence and an i-th data item of the first data sequence. The method further includes outputting the permuted second data sequence.

公开(公告)号：EP1367730B1

公开(公告)日：2018-03-28

申请号：EP03019292.6

申请日：2000-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kim, Min-Goo ,  Kim, Beong-Jo Shinan Apt. 303-804 ,  Choi, Soon-Jae ,  Lee, Young-Hwan

IPC: H03M13/27 ,  H03M13/29

CPC classification number: H03M13/2771 ,  G11B2220/2562 ,  H03M13/27 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/276 ,  H03M13/2764 ,  H03M13/2957

Abstract: A 2-dimensional interleaving method is disclosed. The method comprises dividing a frame of input information bits into a plurality of groups and sequentially storing the divided groups in a memory; permuting the information bits of the groups according to a given rule and shifting an information bit existing at the last position of the last group to a position preceding the last position; and selecting the groups according to a predetermined order, and selecting one of the information bits in the selected group.

公开(公告)号：EP2728754A1

公开(公告)日：2014-05-07

申请号：EP12191152.3

申请日：2012-11-02

Applicant: BlackBerry Limited

Inventor： Stafford, Christopher

IPC: H03M13/27 ,  H03M13/29

CPC classification number: H03M13/2739 ,  H03M13/2764 ,  H03M13/2957 ,  H03M13/6525

Abstract: The present disclosure concerns an interleaver according to the 3GPP-LTE standard turbo interleaving function whereby interleaved bit sequence locations are generated from successive bit sequence locations of a bit sequence. The interleaved bit location is derived iteratively using a new first counter value of a first counter based on a current value of the first counter and a first function derived from an interleaver bit sequence function which relates an interleaved bit sequence location to a bit sequence location. A new second counter value of a second counter is then derived based on a current value of the second counter and the first counter. Finally, an interleaved bit sequence location is output based on the value of the second counter.

Abstract translation: 本公开涉及根据3GPP-LTE标准turbo交织功能的交织器，由此从比特序列的连续比特序列位置生成交织比特序列位置。 基于第一计数器的当前值和从交织器比特序列函数导出的第一函数，迭代地使用第一计数器的新的第一计数器值来导出交错比特位置，该交织器比特序列功能将交织的比特序列位置与比特序列位置相关联。 然后基于第二计数器和第一计数器的当前值导出第二计数器的新的第二计数器值。 最后，基于第二计数器的值输出交织比特序列位置。

公开(公告)号：EP2139120A3

公开(公告)日：2012-09-05

申请号：EP09008223.1

申请日：2009-06-23

Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Inventor： Breiling, Marco

IPC: H03M13/27 ,  H03M13/29

CPC classification number: H03M13/2771 ,  H03M13/271 ,  H03M13/2764 ,  H03M13/2957

Abstract: Interleaver zum Verwürfeln eines Informationswortes, wobei das Informationswort eine Vielzahl von Stellen aufweist, um ein permutiertes Informationswort zu erhalten. Der Interleaver umfasst eine erste Interleaverstufe zum zeilenweisen Anordnen der Stellen des Informationswortes in einer Mehrzahl von ersten Zeilen und ersten Spalten und eine zweite Interleaverstufe zum Verwürfeln der Stellen einer der ersten Zeilen durch vertauschen wenigstens zweier Stellen der einen ersten Zeile, um eine erste verwürfelte Zeile zu erhalten, und zum Ersetzen der einen der ersten Zeilen mit der ersten verwürfelten Zeile. Die erste Interleaverstufe ist ausgebildet, um die basierend auf der ersten verwürfelten Zeile ersetzte erste Zeile spaltenweise auszulesen, um das permutierte Informationswort zu erhalten.

公开(公告)号：EP1650873B1

公开(公告)日：2011-05-11

申请号：EP05026605.5

申请日：1999-02-26

Applicant: Fujitsu Ltd.

Inventor： Ohbuchi, Kazuhisa, Fujitsu Limited ,  Yano, Tetsuya, Fujitsu Limited ,  Kawabata, Kazuo, Fujitsu Limited ,  Nakamura, Takaharu, Fujitsu Limited

IPC: H03M13/29 ,  H03M13/27

CPC classification number: H03M13/2984 ,  H03M13/2707 ,  H03M13/275 ,  H03M13/2764 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2782 ,  H03M13/2785 ,  H03M13/6505 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0071

公开(公告)号：EP2269313A1

公开(公告)日：2011-01-05

申请号：EP09723902.4

申请日：2009-03-17

Applicant: QUALCOMM Incorporated

Inventor： ROSTAMPISHEH, Ali ,  CHALLA, Raghu, N. ,  YAO, Iwen ,  SANTOS, Dave, J. ,  NATH, Mrinal, M.

IPC: H03M13/27

CPC classification number: H03M13/2785 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2775 ,  H03M13/6566

Abstract: A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.

Abstract translation: 解交织器生成多个解交织重排序物理（DRP）地址，以将相应的多个LLR值同时写入多存储区存储器，使得不多于一个LLR值被写入到多存储区的每个存储体中 一次记忆。 这种并行写入的序列导致子分组的传输的LLR值被存储在存储器中。 在生成DRP地址期间执行的地址转换导致LLR值被存储在存储体内，使得解码器可以按照去交织的序列从存储器中读取LLR值。 银行的每个存储位置都是用于存储多个相关LLR值的字位置，其中一个LLR值与其奇偶校验值一起存储。 同时写入多个LLR值的功能用于以快速高效的方式清除位置。

公开(公告)号：EP2129067A2

公开(公告)日：2009-12-02

申请号：EP09251245.8

申请日：2009-05-01

Applicant: Sony Corporation

Inventor： Samuel Asambeng Atungsiri ,  Matthew Paul Athol Taylor

IPC: H04L27/26

CPC classification number: H04L27/2602 ,  H03M13/2742 ,  H03M13/2764 ,  H04L1/0071 ,  H04L27/2647 ,  H04N21/6112

Abstract: A data processing apparatus is operable to map data symbols received from sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols into an output data stream. The data processing apparatus includes an address generator, an interleaver memory and a controller. The controller is operable, when operating in accordance with an even interleaving process to read out from the interleaver memory a first set of the data symbols into the output data stream using addresses generated by the address generator, to write into the interleaver memory a second set of the data symbols received from the sub-carrier signals of an even OFDM symbol using the addresses generated by the address generator. The controller is operable in accordance with an odd interleaving process, to read out from the interleaver memory a first set of the data symbols into the output data stream using read addresses determined in accordance with a sequential order of the first set of data symbols, and to write into the interleaver memory a second set of the data symbols received from the sub-carrier signals of an odd OFDM symbol at write addresses determined in accordance with a sequential order of the first set of input data symbols, such that while data symbols from the first set are being read from locations in the interleaver memory, input data symbols from the second set can be written to the locations just read from. The number of the sub-carriers which are available from a previous OFDM symbol is different from the number of the sub-carriers which are available from a current OFDM symbol, and the controller is operable to determine before reading out the first data symbols from the interleaver memory, whether the read address is valid for the previous OFDM symbol, and to determine before writing the second data symbols into the interleaver memory, whether the write address is valid for the current OFDM symbol. Application can be found with DVB Cable 2, which can provide substantially four thousand carriers.

Abstract translation: 数据处理装置可操作以将从正交频分复用（OFDM）符号的子载波信号接收的数据符号映射到输出数据流。 数据处理装置包括地址发生器，交织器存储器和控制器。 控制器可操作，当根据偶数交错处理操作时，使用地址发生器生成的地址从交错器存储器读出第一组数据符号到输出数据流中，以将第二组写入交织器存储器 使用由地址发生器产生的地址从偶OFDM符号的副载波信号接收的数据符号。 控制器可根据奇数交错处理操作，使用根据第一组数据符号的顺序确定的读取地址从交织器存储器读出第一组数据符号到输出数据流中，以及 以根据第一组输入数据符号的顺序确定的写入地址，从奇数OFDM符号的子载波信号中接收的第二组数据符号，使得当数据符号从 第一组正在从交织器存储器中的位置读取，来自第二组的输入数据符号可被写入刚被读取的位置。 从先前OFDM符号可获得的子载波的数量不同于从当前OFDM符号可用的子载波的数量，并且控制器可操作以在从第一个OFDM符号读出第一数据符号之前确定 交织器存储器，读地址是否对先前OFDM符号有效，并且在将第二数据符号写入交织器存储器之前确定写地址对于当前OFDM符号是否有效。 可以使用DVB电缆2，可以提供大约四千个运营商的应用。

公开(公告)号：EP1538757B1

公开(公告)日：2007-12-12

申请号：EP05290324.2

申请日：2000-04-11

Applicant: Nortel Networks Limited

Inventor： Tong, Wen ,  Leretaille, Catherine ,  Gosne, Stéphane

IPC: H03M13/00 ,  H03M13/27 ,  H03M13/29 ,  H04L1/00

CPC classification number: H03M13/2739 ,  H03M13/00 ,  H03M13/271 ,  H03M13/275 ,  H03M13/276 ,  H03M13/2764 ,  H03M13/2792 ,  H03M13/2957 ,  H03M13/635 ,  H04L1/0041 ,  H04L1/0052 ,  H04L1/0068 ,  H04L1/0071

Abstract: A method of and apparatus for matching a rate of data bits, in a matrix of data bits interleaved by a predetermined interleaving process (50, 53, 62), to a desired rate by deletion of redundant data bits or repetition of data bits derived from the matrix, includes steps of determining (70) in a non-interleaved matrix of the data bits a pattern of bits to be deleted or repeated to provide the desired data rate, decoding (72) an address of each bit in said pattern in a manner inverse to the interleaving process to produce a respective address of the bit in the matrix of interleaved data bits, and deleting or repeating (76) the respective bit in the interleaved data bits in dependence upon the respective address. The address decoding is performed in the same manner as a coding (53) of addresses for producing the interleaved data bits from the non-interleaved matrix of the data bits. Also disclosed is an advantageous interleaving process for channel interleaving in a 3rd generation CDMA wireless communications system, a shuffling method for a second stage of interleaving in such a system, and how the rate matching can be conveniently applied to turbo-coded data coded.