公开(公告)号：EP1384328A2

公开(公告)日：2004-01-28

申请号：EP02707916.9

申请日：2002-02-26

申请人： QUALCOMM INCORPORATED

发明人： YAO, Iwen ,  SHIU, Da-Shan

IPC分类号： H03M13/00

CPC分类号： H04L5/023 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2789 ,  H03M13/2957 ,  H04L1/005 ,  H04L1/0066

摘要： Techniques to efficiently generate memory addresses for a Turbo code interleaver using a number of look-up tables. An interleaver includes a storage unit, sets of tables, and an address generator. The storage unit stores K elements for a data packet at locations representative of an RxC array, with the elements being stored in a first (e.g., linear) order and provided in a second (e.g., interleaved) order. A first set of table(s) stores sequences (e.g., inter-row permutation sequences PA, PB, PC and PD) used to perform row permutation of the array to map from the first order to the second order. A second set of table(s) stores sequences (e.g., intra-row base sequences and prime number sequences) used to perform column permutation. The address generator receives a first address for the first order and generates a corresponding second address for the second order based on sequences stored in the tables.

公开(公告)号：EP2272005A2

公开(公告)日：2011-01-12

申请号：EP09725649.9

申请日：2009-03-27

申请人： QUALCOMM Incorporated

发明人： CHAUDHURI, Arunava ,  SAMPATH, Hemanth ,  YAO, Iwen ,  LIN, Jeremy, H. ,  CHALLA, Raghu, N. ,  WU, Min

IPC分类号： G06F17/14

CPC分类号： G06F17/142 ,  H04L5/0007 ,  H04L5/0023 ,  H04L5/0053 ,  H04L27/265 ,  H04L27/2662

摘要： An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.

公开(公告)号：EP2274885A1

公开(公告)日：2011-01-19

申请号：EP09726787.6

申请日：2009-03-09

申请人： QUALCOMM Incorporated

发明人： KADOUS, Tamer, A ,  YAO, Iwen ,  WANG, Jibing ,  JING, Weihong ,  LI, Yong

IPC分类号： H04L25/06

CPC分类号： H04L25/061 ,  H03G3/3068 ,  H03G3/3078

摘要： A technique for performing AGC and DC compensation in a receiver. The receiver comprises an energy estimator for generating an estimate of the level of a received signal; an RF device to apply gain to the received signal; an AGC for controlling the RF device gain based on the energy estimation; a first DC compensation loop for finely adjusting the DC component of the received signal in fast or slow tracking mode (FTM or STM); and a second DC compensation loop for coarsely adjusting the DC component of the received signal. Three modes of AGC operations: In Acquisition, iterations of FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during signal timing detection. In Connected, long energy estimation, RF device gain adjustment, and STM fine and coarse DC adjustments are performed during superframe preamble. In Sleep, FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during superframe preamble.

公开(公告)号：EP2266053A1

公开(公告)日：2010-12-29

申请号：EP09725530.1

申请日：2009-03-07

申请人： QUALCOMM Incorporated

发明人： CHAUDHURI, Arunava ,  YAO, Iwen ,  LIN, Jeremy, H. ,  ROSTAMPISHEH, Ali ,  CHALLA, Raghu ,  SAMPATH, Hemanth ,  WU, Megan ,  ZANOTELLI, Joseph ,  NATH, Mrinal

IPC分类号： G06F15/78 ,  H04M1/725

CPC分类号： G06F15/7842

摘要： A flexible and reconfϊgurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub- circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub- circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

摘要翻译： 灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。 每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。 子电路的任务管理器可以配置和控制子电路的可配置硬件。 中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。 每个任务列表包括相应子电路的任务指令。 子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。 时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

公开(公告)号：EP2269313A1

公开(公告)日：2011-01-05

申请号：EP09723902.4

申请日：2009-03-17

申请人： QUALCOMM Incorporated

发明人： ROSTAMPISHEH, Ali ,  CHALLA, Raghu, N. ,  YAO, Iwen ,  SANTOS, Dave, J. ,  NATH, Mrinal, M.

IPC分类号： H03M13/27

CPC分类号： H03M13/2785 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2775 ,  H03M13/6566

摘要： A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.

摘要翻译： 解交织器生成多个解交织重排序物理（DRP）地址，以将相应的多个LLR值同时写入多存储区存储器，使得不多于一个LLR值被写入到多存储区的每个存储体中 一次记忆。 这种并行写入的序列导致子分组的传输的LLR值被存储在存储器中。 在生成DRP地址期间执行的地址转换导致LLR值被存储在存储体内，使得解码器可以按照去交织的序列从存储器中读取LLR值。 银行的每个存储位置都是用于存储多个相关LLR值的字位置，其中一个LLR值与其奇偶校验值一起存储。 同时写入多个LLR值的功能用于以快速高效的方式清除位置。

公开(公告)号：EP2266052A2

公开(公告)日：2010-12-29

申请号：EP09723836.4

申请日：2009-03-07

申请人： QUALCOMM Incorporated

发明人： CHAUDHURI, Arunava ,  YAO, Iwen ,  LIN, Jeremy, H. ,  GURSKI, Remi ,  YEN, Kevin, W.

IPC分类号： G06F15/78 ,  H04M1/725 ,  G06F9/48

CPC分类号： G06F9/3879 ,  G06F15/7814

摘要： A flexible and reconfϊgurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub- circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub- circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

摘要翻译： 灵活和可重新配置的数字系统（例如，无线调制解调器）包括一组子电路。 每个子电路包括任务管理器和用于对数据流执行一种操作的可配置硬件电路的量。 子电路的任务管理器可以配置和控制子电路的可配置硬件。 中央处理器通过在紧耦合存储器中维护一组任务列表来配置和协调子电路的操作。 每个任务列表包括相应子电路的任务指令。 子电路的任务管理器从其任务列表读取任务指令，并根据指令控制其相关联的硬件电路。 时间戳任务指令和推送任务指令以及任务列表架构允许将调制解调器子电路轻松地重新配置为根据第一空中接口标准或第二空中接口标准进行操作。

公开(公告)号：EP1388213A1

公开(公告)日：2004-02-11

申请号：EP02734384.7

申请日：2002-05-09

申请人： QUALCOMM INCORPORATED

发明人： SHIU, Da-Shan ,  YAO, Iwen

IPC分类号： H03M13/27 ,  H03M13/29

CPC分类号： H04L1/005 ,  H03M13/2714 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/6566 ,  H04L1/0055 ,  H04L1/0068 ,  H04L1/0071

摘要： A buffer structure for storing intermediate results (i.e., APP data) for a Turbo decoder. To increase access throughput, the buffer structure is designed to support concurrent access of APP data for two or more bits for each access cycle. This is achieved by partitioning the buffer into a number of banks, with each bank being independently accessible. To avoid access contentions, the banks are assigned to the rows and columns of a 2-dimensional array used for code interleaving such that APP data for consecutive bits are accessed from different banks. To support 'linear' addressing, the banks can be arranged into two sets, which are assigned to even- numbered and odd-number columns of the array. To support 'interleaved' addressing, the banks can be assigned to groups of rows of the array such that adjacent rows in the interleaved array are assigned to different groups.