公开(公告)号：EP1595154A4

公开(公告)日：2006-05-10

申请号：EP03713598

申请日：2003-02-20

申请人： IBM

发明人： GATTIKER ANNE ,  GROSCH DAVID A ,  KNOX MARC D ,  MOTIKA FRANCO ,  NIGH PHIL ,  VAN HORN JODY ,  ZUCHOWSKI PAUL S

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/26

CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3008

摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

公开(公告)号：EP1644748A2

公开(公告)日：2006-04-12

申请号：EP04733617.7

申请日：2004-05-18

申请人： Koninklijke Philips Electronics N.V.

发明人： VEENDRICK, Hendricus, J., M.

IPC分类号： G01R31/30 ,  G01R31/3185

CPC分类号： G01R31/30 ,  G01R31/31722 ,  G01R31/318505 ,  G01R31/319 ,  G11C29/50 ,  G11C2029/3202 ,  G11C2029/5002

摘要： A method suitable for testing an integrated circuit device is disclosed, the device comprising at least one module (47), wherein the at least one module incorporates at least one associated module monitor (49, 51, 53, 55) suitable for monitoring a device parameter such as temperature, supply noise, cross-talk etc. within the module.

摘要翻译： 公开了一种适用于测试集成电路装置的方法，所述装置包括至少一个模块（47），其中所述至少一个模块包含至少一个相关联的模块监视器（49,51,53,55），适合于监视设备 参数如模块内的温度，电源噪声，串扰等。

公开(公告)号：EP1639379A1

公开(公告)日：2006-03-29

申请号：EP04735779.3

申请日：2004-06-02

申请人： Koninklijke Philips Electronics, N.V.

发明人： PESSOLANO, Francesco ,  THEUNISSEN, Bob, B., A.

IPC分类号： G01R31/30 ,  G06F11/24

CPC分类号： G01R31/31727 ,  G01R31/31725 ,  G01R31/31922 ,  G06F11/24

摘要： An integrated circuit 1 comprises a timing closure monitoring circuit 2. The timing closure monitoring circuit 2 comprises a duplicate path 19, having the same characteristics as a logic path 3 being monitored. The duplicate path 19 receives a pulsed reference signal 23 from a reference generating unit (RGU) 24. The pulsed reference signal 23 is synchronized with the clock signal 13, and passed through the duplicate path 19 to a reference checking unit (RCU) 25. In a normal mode of operation in which timing closure is guaranteed, the clock signal 13 will sample the pulsed reference signal 23, such that no interrupt signal is generated on the interrupt line 33. However, in the situation where the reference check unit 25 is clocked by the clock signal 13 prior to the pulsed reference signal 23 being received via the duplicate path 19, an interrupt signal is generated on the interrupt line 33, indicating that timing closure cannot be guaranteed.

公开(公告)号：EP1583007A3

公开(公告)日：2005-10-26

申请号：EP05000924.0

申请日：2005-01-18

申请人： Renesas Technology Corp.

发明人： Ibe, Hidefumi Hitachi, Ltd. ,  Yahagi, Yasuo Hitachi, Ltd. ,  Kameyama, Hideaki Hitachi, Ltd.

IPC分类号： G06F17/50 ,  G11C11/412 ,  G06F17/18 ,  G01R31/30

CPC分类号： G01R31/31816 ,  G01R31/002 ,  G01R31/2849 ,  G01R31/2881 ,  G01R31/30

摘要： When resistivity against errors caused by cosmic ray neutrons in a semiconductor device is evaluated, the storage (120) in the evaluation apparatus stores multiple spectrum data of white neutrons having different spectrum shapes, and multiple SEE counts obtained by the white neutron method using this multiple spectrum data. A computing section (100) performs processing, with respect to each spectrum data, to read out the spectrum data from the storage, divide the data into multiple energy groups, calculates and stores a total flux of each energy group. Furthermore, the computing section reads out from the storage, the SEE counts with respect to each of the multiple spectrum data and the total flux of each energy group, substitutes the SEE counts and the total flux into a simultaneous equation, where a product of matrix elements indicating the total flux of each of the energy groups as to each of the multiple spectrum data and vectors indicating the SEE cross section of each of the energy groups represents the SEE count as to each of the multiple spectrum data, and calculates the SEE cross section for each of the energy groups. Subsequently, the computing section performs a calculation so that parameters are calculated, which determine a formula of the approximate function of the SEE cross section as a function of energy, so that computed values of error counts obtained by integration of multiple spectra and the approximate function sufficiently match the actual measured values thereof. With the processing as described above, there has been achieved an error evaluation in the semiconductor device using white neutrons independent from an accelerator.

摘要翻译： 当针对通过在半导体器件中的宇宙射线的中子引起的错误的电阻率进行评价，在评价装置中的存储装置（120）存储具有不同的频谱形状通过使用该多个白色中子方法得到的白色中子的多个频谱数据和多个SEE计数 光谱数据。 一种计算部（100）执行处理，对于每个光谱数据，从存储读出的谱数据，将数据划分为多个能量组，计算和存储各能量组的总通量。 进一步，运算部从存储中读出时，SEE相对于每个所述多个谱数据和每个能量组的总通量的计数，代入SEE计数和总光通量成的联立方程，矩阵的其中一个产品 关于每个所述多个谱数据和向量元素指示每个能量组的总通量指示每个能量组的SEE截面darstellt的SEE数作为给每个所述多个谱数据，并且计算SEE横 部针对每个能量组。 接着，运算部进行运算所以没有参数被计算，其中确定性矿作为能量的函数的SEE截面的近似函数的公式，所以并计算由多个光谱的积分和近似函数而获得的错误计数的值 充分匹配其实际测量值。 通过如上所述的处理，存在一种使用白色中子从独立于加速器已经达到在误差评价的半导体装置。

公开(公告)号：EP1504273A1

公开(公告)日：2005-02-09

申请号：EP03720566.3

申请日：2003-05-14

申请人： Infineon Technologies AG

发明人： ARNOLD, Ralf ,  HEINITZ, Matthias ,  KÖPPE, Siegmar ,  SCHÖBER, Volker

IPC分类号： G01R31/30 ,  G01R31/3185 ,  G01R31/3181 ,  G01R31/3183

CPC分类号： G01R31/3183 ,  G01R31/31813 ,  G01R31/318547

摘要： The invention relates to a system for testing digital components comprising functional elements. According to said invention, said functional elements are divided into test units (3) which respectively comprise inputs and outputs. The inputs of the test units (3) are impinged upon by alternating test patterns and the test responses thus obtained are evaluated at the outputs of said units (3). As a result, modifications at all outputs of a test unit (3) do not influence a specific output of said test unit (3). A cone (5) can be defined for each output of the test unit (3), whereby the tip thereof is formed by the specific output of the test unit (3) and the base thereof comprises the inputs of the test unit (3) whereon only the modifications influence the specific output. According to the invention, the test pattern for impinging upon the inputs of the test unit (3) is made up of sub-patterns, whereby the length thereof is particularly = according to the number of inputs of the test unit (3) contained in the base of the cone (5). During the selection of the sub patterns, all possible combinations can be used according to the reduced length thereof such that an extensive functional control of the test unit (3) can be carried out with reduced effort. Said test function can be implemented in a digital component, especially by means of an automatic-test unit (1) which can switch the remainder of the digital components into a test mode and which can produce the test patterns on the basis of the sub-patterns, loading them into a test pattern output register (2), and evaluating reading for evaluating the test response obtained at the outputs of the test unit (3) by means of an evaluation unit (16).

公开(公告)号：EP1190264B1

公开(公告)日：2005-01-19

申请号：EP00927200.6

申请日：2000-05-12

申请人： Infineon Technologies AG

发明人： WEDER, Uwe

IPC分类号： G01R31/30 ,  G11C29/00

CPC分类号： G01R31/3004 ,  G11C29/50

摘要： The invention relates to an integrated circuit and to a method for determining the current yield of a part of the integrated circuit. According to the invention, the current yield of at least one circuit part (ST) of the integrated circuit (IS) is determined by measuring the current yield of a current source (T1, T2, T3, T4) which is arranged on an input terminal (EA1, EA2) or output terminal (AA1), whose current yield is proportionate, in a defined manner, to a number of reference current sources (REF0...REF7) which are located inside the circuit and which have different current yields, and whose current yield is compared with that of the circuit part (ST) to be measured. By knowing which of the internal reference current sources (REF0...REF7) have a higher and which have a lower current yield than that of the circuit part (ST) to be measured, and by knowing the current yield of the current sources (T1, T2, T3, T4) arranged on an input terminal (EA1, EA2) or output terminal (AA1) as well as by knowing the proportion of the current yields, the current yield of the circuit part (ST) can be measured without directly accessing the integrated circuit (IS) from outside.

公开(公告)号：EP1367403A3

公开(公告)日：2004-10-27

申请号：EP03447122.7

申请日：2003-05-23

申请人： Q-Star Test N.V.

发明人： Manhaeve, Hans ,  De Pauw, Piet

IPC分类号： G01R31/30

CPC分类号： G01R31/3004 ,  G01R31/3008

摘要： The present invention is related to a method for testing a micro-electronic device, by applying a plurality of test vectors to said device, and measuring for each test vector, the quiescent supply current I DDQ , to said device, wherein each I DDQ measured value is divided by another I DDQ value, and wherein the result of said division is compared to a predefined reference, resulting in a pass or fail decision for said device.

公开(公告)号：EP0953848B1

公开(公告)日：2004-07-28

申请号：EP99102191.6

申请日：1999-02-04

申请人： Micronas GmbH

发明人： Hummel, Ulrich Helmut, Dipl.-Ing.

IPC分类号： G01R31/30 ,  G11C29/00

CPC分类号： H01L22/22

公开(公告)号：EP1129408B1

公开(公告)日：2004-07-14

申请号：EP00956500.3

申请日：2000-08-30

申请人： Koninklijke Philips Electronics N.V.

发明人： MELI, Louis, M.

IPC分类号： G06F11/267 ,  G01R31/30

CPC分类号： G06F11/2236 ,  G01R31/3004 ,  G06F2201/88

摘要： The microcomputer has an instruction memory interface that applies instructions to an instruction execution unit. In a normal state instructions are obtained from instruction memory under control of a normal program counter. In a test state a same source of an instruction is used cyclically to apply a same instruction information from a test instruction memory. Normal addressing is suppressed in the test state, so that the same instruction is executed repeatedly independent of normal program flow.

摘要翻译： 微型计算机有一个指令存储器接口，用于向指令执行单元提供指令。 在正常状态下，指令是在正常程序计数器的控制下从指令存储器获得的。 在测试状态下，周期性地使用相同的指令源来从测试指令存储器施加相同的指令信息。 正常寻址在测试状态下被抑制，以便相同的指令被重复执行而不依赖于正常的程序流程。

公开(公告)号：EP1306681A3

公开(公告)日：2004-03-03

申请号：EP02102220.7

申请日：2002-08-27

申请人： Philips Intellectual Property & Standards GmbH ,  Koninklijke Philips Electronics N.V.

发明人： Schäfer, Martin ,  Wichern, Andreas

IPC分类号： G01R31/30 ,  G01R31/316 ,  G01R31/27

CPC分类号： H01L22/34 ,  G01R31/3275

摘要： Bei einem Verfahren und einer Anordnung zur Ermittlung des Hochfrequenzverhaltens von aktiven Schaltungselementen in auf einer Substratscheibe befindlichen Schaltungen, wobei stellvertretend für die aktiven Schaltungselemente in den Schaltungen aktive Schaltungselemente in ebenfalls auf der Substratscheibe befindlichen Prozeßkontrollmodulen benutzt werden, wird die Schwingfrequenz von in den Prozeßkontrollmodulen enthaltenen aus aktiven Schaltungselementen aufgebauten Ringoszillatoren gemessen und ausgewertet.