公开(公告)号：EP2688207B1

公开(公告)日：2017-12-13

申请号：EP11860939.5

申请日：2011-03-16

申请人： Fujitsu Limited

发明人： SUZUKI, Toshihide ,  KAWANO, Yoichi

IPC分类号： H03H11/28 ,  G01R31/28 ,  H03H7/38 ,  H03K19/0175 ,  H04B1/04 ,  H04B3/02

CPC分类号： G01R31/3183 ,  G01R31/2822 ,  H03F1/56 ,  H03F2200/387 ,  H03H11/30 ,  H03K17/161 ,  H04B1/0458 ,  H04L25/0278 ,  H04L25/0298

摘要： A termination circuit includes a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function; and an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance.

公开(公告)号：EP3098957A2

公开(公告)日：2016-11-30

申请号：EP16167628.3

申请日：2016-04-29

申请人： Delta Electronics, Inc.

发明人： ZHOU, Jian-Hong ,  LU, Cheng ,  ZHANG, Jia-Min ,  WU, Hong-Yang

IPC分类号： H02M7/00

CPC分类号： G01R27/26 ,  G01R27/06 ,  G01R27/28 ,  G01R31/3183 ,  H02M7/44 ,  H02M7/5387 ,  H02M2001/0003

摘要： A detecting method for detecting an output impedance angle of an inverter includes controlling an inverter to output a second voltage signal and a current signal based on a first voltage signal; calculating an active power and reactive power based on the second voltage signal and the current signal; and calculating an output impedance angle of the inverter based on the product of the active power and a first amplitude parameter, the product of the active power and a second amplitude parameter, the product of the reactive power and the first amplitude parameter, and the product of the reactive power and the second amplitude parameter. The first amplitude parameter corresponds to a first amplitude of the first voltage signal, and the second amplitude parameter corresponds to the first amplitude of the first voltage signal and a second amplitude of an AC voltage.

摘要翻译： 用于检测逆变器的输出阻抗角的检测方法包括控制逆变器以基于第一电压信号输出第二电压信号和电流信号; 基于第二电压信号和当前信号计算有功功率和无功功率; 以及基于所述有功功率和第一振幅参数的乘积，所述有功功率与第二振幅参数的乘积，所述无功功率与所述第一振幅参数的乘积以及所述乘积来计算所述逆变器的输出阻抗角 的无功功率和第二振幅参数。 第一幅度参数对应于第一电压信号的第一幅度，第二幅度参数对应于第一电压信号的第一幅度和交流电压的第二幅度。

公开(公告)号：EP1376417B1

公开(公告)日：2016-09-07

申请号：EP03291452.5

申请日：2003-06-16

申请人： SYNOPSYS EMULATION AND VERIFICATION

发明人： Bergun, Luc ,  Reynier, David ,  Delerse, Sébastien ,  Emirian, Frédéric ,  Douezy, François

IPC分类号： G06F11/26 ,  G01R31/3183 ,  G06F17/50

CPC分类号： G01R31/318314 ,  G01R31/3183 ,  G01R31/318357 ,  G06F11/261 ,  G06F17/5027

公开(公告)号：EP1717711B1

公开(公告)日：2015-04-01

申请号：EP05709897.2

申请日：2005-02-08

申请人： ANRITSU CORPORATION

发明人： KUMAKI, Akihisa ,  HANAYA, Tatsuro

IPC分类号： G06F21/10 ,  G01R31/3183

CPC分类号： G06F21/105 ,  G01R31/3183 ,  G06F21/10

公开(公告)号：EP2331979B1

公开(公告)日：2012-07-04

申请号：EP09787305.3

申请日：2009-09-26

申请人： NXP B.V.

发明人： JONG, Fransciscus Gerardus Maria De ,  BIEWENGA, Alexander, Sebastian

IPC分类号： G01R31/3185

CPC分类号： G01R31/318555 ,  G01R19/00 ,  G01R31/26 ,  G01R31/28 ,  G01R31/31717 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/318558 ,  G01R31/31924

摘要： The present invention discloses a method of testing a partially assembled multi-die device (1) by providing a carrier (300) comprising a device-level test data input (12) and a device-level test data output (18); placing a first die on the carrier, the first die having a test access port (100c) comprising a primary test data input (142), a secondary test data input (144) and a test data output (152), the test access port being controlled by a test access port controller (110); communicatively coupling the secondary test data input (144) of the first die to the device-level test data input (12), and the test data output (152) of the first die to the device-level test data output (18); providing the first die with configuration information to bring the first die in a state in which the first die accepts test instructions from its secondary test data input (144); testing the first die, said testing including providing the secondary test data input (144) of the first die with test instructions through the device-level test data input (12); and collecting a test result for the first die on the device-level test data output (18). Consequently, a die of a partially assembled multi-die device such as a System-in-Package may be tested using its integrated boundary scan test architecture.

公开(公告)号：EP2113087A1

公开(公告)日：2009-11-04

申请号：EP07713151.4

申请日：2007-02-16

申请人： Freescale Semiconductor, Inc.

发明人： SAKADA, Oleksandr ,  BOGENBERGER, Florian

IPC分类号： G01R31/3187 ,  G01R31/3183 ,  G06F11/27

CPC分类号： G06F11/27 ,  G01R31/005 ,  G01R31/007 ,  G01R31/3183 ,  G01R31/3187

摘要： A system (25) for testing a logic circuit (20) which has two or more test routine modules (27). Each module contains a set of instructions which is executable by (a part of) the logic circuit (20). The set forms a test routine for performing a self-test by the part of the logic circuit (20). The self-test includes the part of the logic circuit (20) testing itself for faulty behaviour, and the part of the logic circuit (20) determining a self-test result of the testing. The system (25) includes a test module which can execute a test application which subjects the logic circuit (20) to a test by performing the self-test on at least a part of the logic circuit (20) by causes the part of the logic circuit (20) to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine. At a test module output interface the overall test result may be outputted. The test routine includes instructions for outputting, by the part of the logic circuit (20), data to a test routine output interface which is not connected to the second test module input interface, for outputting information about the self-test result by the test routines without passing the information through the test module.

公开(公告)号：EP1756603B1

公开(公告)日：2009-08-05

申请号：EP05743357.5

申请日：2005-05-23

申请人： ADVANTEST CORPORATION

发明人： PRAMANICK, Ankan ,  ELSTON, Mark ,  ADACHI, Toshiaki

IPC分类号： G01R31/319

CPC分类号： G01R31/31907 ,  G01R31/3183 ,  G01R31/318307 ,  G01R31/318342

摘要： A method for integrating test modules in a modular test system is disclosed. The method includes controlling at least one test module and its corresponding device under test, DUT, with a controller, establishing a standard module control interface between a vendor-supplied test module and the modular test system with a module control framework, installing the vendor-supplied test module and a corresponding vendor-supplied control software module, where the vendor-supplied control software module is organized into a plurality of vendor-supplied module control components, configuring the modular test system based on the module control framework and the plurality of vendor-supplied module control components, and accessing the vendor-supplied test module in accordance with the plurality of vendor-supplied module control components using the module control framework.

公开(公告)号：EP1747617A2

公开(公告)日：2007-01-31

申请号：EP05744211.3

申请日：2005-05-02

申请人： DFT Microsystems, Inc.

发明人： HAFED, Mohamed, M. ,  DUERDEN, Geoffrey, D. ,  ROBERTS, Gordon, W.

IPC分类号： H04B3/46

CPC分类号： H04B3/462 ,  G01R31/31709 ,  G01R31/31725 ,  G01R31/3183 ,  G01R31/31917

摘要： A multi-speed jittered signal generator (216,400) that generates a full-speed jittered signal (404) by scaling a low-speed jittered signal (420) using a frequency scaler (428). The low-speed jittered signal is created by injecting a modulation signal (416) into a reference signal (412) using a jitter injector (432). Injecting jitter into a low-speed reference signal allows the full-speed jittered signal to be of higher quality than conventional jitter signals created by injecting jitter information into a full-speed reference signal. The multi-speed jittered signal generator may be used as part of a testing system (208) for testing various circuitry, such as high-speed serializer/deserializer circuitry (220).

公开(公告)号：EP1504273B1

公开(公告)日：2005-10-12

申请号：EP03720566.3

申请日：2003-05-14

申请人： Infineon Technologies AG

发明人： ARNOLD, Ralf ,  HEINITZ, Matthias ,  KÖPPE, Siegmar ,  SCHÖBER, Volker

IPC分类号： G01R31/30 ,  G01R31/3185 ,  G01R31/3181 ,  G01R31/3183

CPC分类号： G01R31/3183 ,  G01R31/31813 ,  G01R31/318547

摘要： The invention relates to a system for testing digital components comprising functional elements. According to said invention, said functional elements are divided into test units (3) which respectively comprise inputs and outputs. The inputs of the test units (3) are impinged upon by alternating test patterns and the test responses thus obtained are evaluated at the outputs of said units (3). As a result, modifications at all outputs of a test unit (3) do not influence a specific output of said test unit (3). A cone (5) can be defined for each output of the test unit (3), whereby the tip thereof is formed by the specific output of the test unit (3) and the base thereof comprises the inputs of the test unit (3) whereon only the modifications influence the specific output. According to the invention, the test pattern for impinging upon the inputs of the test unit (3) is made up of sub-patterns, whereby the length thereof is particularly = according to the number of inputs of the test unit (3) contained in the base of the cone (5). During the selection of the sub patterns, all possible combinations can be used according to the reduced length thereof such that an extensive functional control of the test unit (3) can be carried out with reduced effort. Said test function can be implemented in a digital component, especially by means of an automatic-test unit (1) which can switch the remainder of the digital components into a test mode and which can produce the test patterns on the basis of the sub-patterns, loading them into a test pattern output register (2), and evaluating reading for evaluating the test response obtained at the outputs of the test unit (3) by means of an evaluation unit (16).

摘要翻译： 本发明涉及用于测试包括功能元件的数字组件的系统。 根据所述发明，所述功能元件被分成测试单元（3），它们分别包括输入和输出。 测试单元（3）的输入通过交替的测试模式而受到影响，并且由此获得的测试响应在所述单元（3）的输出处被评估。 结果，测试单元（3）的所有输出处的修改不影响所述测试单元（3）的特定输出。 可以为测试单元（3）的每个输出端定义一个锥体（5），由此其尖端由测试单元（3）的特定输出端形成，并且其基部包括测试单元（3）的输入端， 其中只有修改影响具体产出。 根据本发明，用于撞击测试单元（3）的输入端的测试图案由子图案组成，由此其长度特别地=根据包含在测试单元（3）中的测试单元（3）的输入的数量 锥体（5）的底部。 在选择子图案期间，可以根据其减小的长度使用所有可能的组合，使得测试单元（3）的广泛的功能控制可以以减少的努力执行。 所述测试功能可以在数字组件中实现，特别是通过自动测试单元（1）来实现，该自动测试单元（1）可以将数字组件的其余部分切换到测试模式并且可以基于子测试结果产生测试模式， 将它们加载到测试模式输出寄存器（2）中，并且通过评估单元（16）评估用于评估在测试单元（3）的输出处获得的测试响应的读数。

公开(公告)号：EP1186901A3

公开(公告)日：2005-06-22

申请号：EP01115838.3

申请日：2001-06-28

申请人： Infineon Technologies AG

发明人： Ernst, Wolfgang ,  Krause, Gunnar ,  Kuhn, Justus ,  Luepke, Jens ,  Mueller, Jochen ,  Poechmueller, Peter ,  Schittenhelm, Michael

IPC分类号： G11C29/00

CPC分类号： G11C29/10 ,  G01R31/3183

摘要： Die Erfindung betrifft ein Verfahren und eine Vorrichtung zur Erzeugung von digitalen Signalmustern, wobei in einem adressierbaren Speicher (1) gespeicherte Signalmuster ausgelesen und zur Verfügung gestellt werden. Bei der Erfindung werden Signalmuster oder Signalmustergruppen (HSC1 - HSC4) in einem sehr kleinen Zwischenspeicher-Register (1) abgelegt. Zusammen mit jedem Signalmuster oder jeder Signalmustergruppe wird in Form einer Sprungadresse auch die Position (BSA) eines folgenden Signalmusters oder einer folgenden Signalmustergruppe abgelegt. Eine einfache Steuerlogikschaltung (2) empfängt ein Steuersignal (S) und bestimmt, ob fortlaufend der Inhalt der aktuell adressierten Gruppe oder nach vollständiger Ausgabe der aktuell ausgewählten Gruppe die durch die im Register (1) gespeicherte Sprungadresse angegebene folgende Gruppe ausgegeben wird. Das erfindungsgemäße Verfahren und die Vorrichtung läßt sich vorteilhaft für den Test von Halbleiterspeichern verwenden und in einem von einem herkömmlichen Testsystem abgesetzten preiswerten Halbleiterschaltkreis (BOST) realisieren.