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31.发明公开VERFAHREN ZUM BETRIEB EINES IMPULSGENERATORS FÜR KAPAZITIVE SENSOREN UND IMPULSGENERATOR 审中-公开电容式传感器和脉冲发生器的脉冲发生器的操作方法
公开(公告)号：EP3257156A1
公开(公告)日：2017-12-20
申请号：EP16700592.5
申请日：2016-01-14
申请人： IFM Electronic GmbH
发明人： SCHULZ, Jörg
CPC分类号： H03K5/06 , H03K5/05 , H03K5/156 , H03K5/26 , H03K2005/00026 , H03K2005/00058
摘要： The invention relates to a method for operating a pulse generator (1) for generating measuring pulses for a capacitive sensor having an adjustable pulse time in the range from 10 ns to 200 ns, having a controllable delay circuit (2) which contains a first integrating RC combination (RT1/CT1) and a second integrating RC combination (RT2/CT2), having a logical combining element (3) having two inputs and one output, an initialization circuit (5) and a control unit (4), wherein the first input of the logical combining element (3) receives a clock signal, and the second input of the logical combining element (3) receives an analog setting signal (SSE) from the output of the delay circuit (2), wherein two simultaneous clock signals are generated, of which the first clock signal (T) is led without delay to the first input of the logical combining element (3), and the second clock signal (T2), delayed by the delay circuit (2), is led to the second input of the logical combining element (3), time-variable output pulses are generated with the aid of time-variable preloading signals (VL), wherein the output from the delay circuit (2) after each measuring pulse is discharged or charged by the initialization switch (5).
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32.发明公开METHOD AND APPARATUS FOR GENERATING OSCILLATOR SIGNALS 审中-公开VERFAHREN UND VORRICHTUNG ZUR ERZEUGUNG VON OSZILLATORSIGNALEN
公开(公告)号：EP3075078A4
公开(公告)日：2017-08-02
申请号：EP13898246
申请日：2013-11-28
CPC分类号： G06F1/02 , H03K5/05 , H03K5/06 , H03K5/131 , H03K5/14 , H03L7/0814 , H03L7/16 , H03L2207/50
摘要： There are disclosed various methods and apparatuses for generating oscillator signals.In some embodiments the method comprises receiving a reference clock signal;obtaining a set of phase shifted reference clock signals; obtaining a phase selection control;using a most significant part of the phase selection control to select one of the phase shifted reference clock signals; and using a least significant part of the phase selection control to delay the selected phase shifted reference clock signal.
摘要翻译： 公开了用于产生振荡器信号的各种方法和设备。在一些实施例中，该方法包括：接收参考时钟信号;获得一组相移参考时钟信号; 获得相位选择控制;使用相位选择控制的最高有效部分来选择相移的参考时钟信号中的一个; 并且使用相位选择控制的最低有效部分来延迟所选择的相移的参考时钟信号。
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公开(公告)号：EP2525490A3
公开(公告)日：2013-12-18
申请号：EP12167823.9
申请日：2012-05-14
申请人： NXP B.V.
发明人： Splithof, Mike , Schapendonk, Edwin
IPC分类号： H03K5/04 , H03K5/05 , H03K5/1252
CPC分类号： H03K5/04 , H03K5/05 , H03K5/1252
摘要： In one embodiment, a circuit-based apparatus (200) that operates on an input data stream (205) includes delay-line circuitry (215) that characterizes the input data stream (205), modified over time. A plurality of integrators (225) provide a plurality of integrated signals in response to the delay-line circuitry (215), and a plurality of weighting amplifiers (235) amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit (240) combines the weighted signals. The circuit-based apparatus (200) also includes a plurality of parallel signal-processing circuit paths (210) that couple the weighted signals to the signal-combining circuit (240). By combining the weighted signals from the parallel signal-processing circuit paths (210), the signal-combining circuit (240) provides a signal representative of the input data stream (205).
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公开(公告)号：EP2525490A2
公开(公告)日：2012-11-21
申请号：EP12167823.9
申请日：2012-05-14
申请人： NXP B.V.
发明人： Splithof, Mike , Schapendonk, Edwin
IPC分类号： H03K5/04 , H03K5/05 , H03K5/1252
CPC分类号： H03K5/04 , H03K5/05 , H03K5/1252
摘要： In one embodiment, a circuit-based apparatus (200) that operates on an input data stream (205) includes delay-line circuitry (215) that characterizes the input data stream (205), modified over time. A plurality of integrators (225) provide a plurality of integrated signals in response to the delay-line circuitry (215), and a plurality of weighting amplifiers (235) amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit (240) combines the weighted signals. The circuit-based apparatus (200) also includes a plurality of parallel signal-processing circuit paths (210) that couple the weighted signals to the signal-combining circuit (240). By combining the weighted signals from the parallel signal-processing circuit paths (210), the signal-combining circuit (240) provides a signal representative of the input data stream (205).
摘要翻译： 在一个实施例中，对输入数据流（205）进行操作的基于电路的设备（200）包括表征随时间变化的输入数据流（205）的延迟线电路（215）。 多个积分器（225）响应于延迟线电路（215）提供多个积分信号，并且多个加权放大器（235）通过多个相应的时变加权因子放大多个积分信号 提供加权信号。 信号组合电路（240）组合加权信号。 基于电路的设备（200）还包括将加权信号耦合到信号组合电路（240）的多个并行信号处理电路路径（210）。 通过组合来自并行信号处理电路路径（210）的加权信号，信号组合电路（240）提供表示输入数据流（205）的信号。
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35.发明授权
公开(公告)号：EP0507471B1
公开(公告)日：1996-06-12
申请号：EP92302358.4
申请日：1992-03-19
申请人： TEKTRONIX INC.
CPC分类号： H03K5/133 , H03K2005/00156 , H03K2005/00163
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公开(公告)号：EP0382233B1
公开(公告)日：1994-08-10
申请号：EP90102565.0
申请日：1990-02-09
申请人： FUJITSU LIMITED
IPC分类号： H03K5/05
CPC分类号： H03K5/05
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37.发明公开Timer circuit including an analog ramp generator and a CMOS counter 失效Taktgeberschaltung beinhaltend einen analogen Rampengenerator und CMOS-Zähler。
公开(公告)号：EP0507471A2
公开(公告)日：1992-10-07
申请号：EP92302358.4
申请日：1992-03-19
申请人： TEKTRONIX INC.
CPC分类号： H03K5/133 , H03K2005/00156 , H03K2005/00163
摘要： A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp timing control signal, and an output for providing a ramp signal. A comparator has a first input coupled to the output of the ramp generator, a second input coupled to a reference voltage source, and an output for providing an end ramp signal. A counter circuit has a first input for receiving the end ramp signal to begin counting, a second input for receiving a counter timing control signal, and an output for providing a terminal count signal. The end ramp signal and the terminal count signal are combined in an AND gate to provide a signal that is delayed by a predetermined amount from the input signal.
摘要翻译： 定时器电路提供宽范围的精确和基本准确的时间间隔。 定时器电路包括斜坡发生器电路，其具有用于接收输入信号以启动斜坡信号的第一输入端，用于接收斜坡时序控制信号的第二输入端和用于提供斜坡信号的输出端。 比较器具有耦合到斜坡发生器的输出端的第一输入端，耦合到参考电压源的第二输入端和用于提供端点斜坡信号的输出端。 计数器电路具有用于接收结束斜坡信号以开始计数的第一输入端，用于接收计数器定时控制信号的第二输入端和用于提供端子计数信号的输出端。 结束斜坡信号和终端计数信号在与门组合以提供从输入信号延迟预定量的信号。
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公开(公告)号：EP0466110A1
公开(公告)日：1992-01-15
申请号：EP91111426.2
申请日：1991-07-09
IPC分类号： H03K5/05
CPC分类号： H03K5/05
摘要： A semiconductor device for driving a light emitting element used in high speed optical communication. The semiconductor device comprises circuitry for delaying a clock signal and producing first and second delay signals. The second delay signal has a delay time different from that of the first delay signal. The first delay signal controls flip-flop circuitry which receives a data signal and outputs a signal indicative of the data signal. The first delay signal also controls a first latch circuit to receive the signal from the flip-flop circuitry and output a signal with the delay time of the first delay signal. The second delay signal controls a second latch circuit to receive the signal from the flip-flop circuitry and output a signal with the delay time of the second delay signal. The signals output from the first and second latch circuits are logically combined by logic circuitry. The logic circuitry is either AND or OR circuitry. The logic circuitry outputs the result of the combination to driving circuitry which provides the current to drive the light emitting element in accordance with the output of the logic circuitry.
摘要翻译： 一种用于驱动用于高速光通信的发光元件的半导体器件。 半导体器件包括用于延迟时钟信号并产生第一和第二延迟信号的电路。 第二延迟信号具有与第一延迟信号不同的延迟时间。 第一延迟信号控制接收数据信号并输出指示数据信号的信号的触发器电路。 第一延迟信号还控制第一锁存电路以接收来自触发器电路的信号并输出具有第一延迟信号的延迟时间的信号。 第二延迟信号控制第二锁存电路以接收来自触发器电路的信号，并输出具有第二延迟信号的延迟时间的信号。 从第一和第二锁存电路输出的信号由逻辑电路逻辑组合。 逻辑电路是AND或OR电路。 逻辑电路将组合的结果输出到根据逻辑电路的输出提供电流驱动发光元件的驱动电路。
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公开(公告)号：EP0089596B1
公开(公告)日：1986-06-25
申请号：EP83102516.8
申请日：1983-03-15
CPC分类号： H03K5/1502 , G06F1/04 , H03K5/15066 , H03K5/15093
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公开(公告)号：EP0089596A1
公开(公告)日：1983-09-28
申请号：EP83102516.8
申请日：1983-03-15
CPC分类号： H03K5/1502 , G06F1/04 , H03K5/15066 , H03K5/15093
摘要： Digital timing unit for timing data processing systems or units thereof, wherein the output signals of a shift register are applied to a plurality of EXCLUSIVE OR gates (G 1 ) .... (G n ).
The shift register, at first in a known status, is activated so that an electrical transition is shifted through the register cells and defines a timing cycle, at the end of which the register is set in a second known status.
A feedback and control logic (3, 4, 5, 6, 7, 8, 9) allows to activate the register independently from its status and to keep it in the status occuring at the end of a timing cycle until a new start signal is received.
The shift of the register is caused by timing pulses generated by an oscillator (1).
The timing signals generated by the timing unit and present on the outputs of the EXCLUSIVE OR may be modified, as to the length, by changing the oscillator period and/or the connection between the EXCLUSIVE OR inputs and the outputs of the shift register.摘要翻译： 用于定时数据处理系统或其单元的数字定时单元，其中移位寄存器的输出信号被施加到多个独占或门（G1）....（Gn）。 首先处于已知状态的移位寄存器被激活，使得电转换通过寄存器单元移位并且定义定时周期，其结束时寄存器被设置在第二已知状态。 ...反馈和控制逻辑（3,4,5,6,7,8,9）允许独立于其状态激活寄存器，并使其保持在定时周期结束时发生的状态，直到 接收到一个新的启动信号。 ...寄存器的移位是由振荡器（1）产生的定时脉冲引起的。 ...由定时单元生成并存在于EXCLUSIVE OR的输出上的定时信号可以通过改变振荡器周期和/或EXCLUSIVE OR输入与输出之间的连接来修改长度 移位寄存器。
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