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公开(公告)号：EP0464524B1
公开(公告)日：1996-03-06
申请号：EP91110273.9
申请日：1991-06-21
IPC分类号： H03K19/094 , H03K19/003
CPC分类号： H03K19/09436 , H03K3/356034 , H03K19/00361 , H03K19/01707
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公开(公告)号：EP0466110A1
公开(公告)日：1992-01-15
申请号：EP91111426.2
申请日：1991-07-09
IPC分类号： H03K5/05
CPC分类号： H03K5/05
摘要： A semiconductor device for driving a light emitting element used in high speed optical communication. The semiconductor device comprises circuitry for delaying a clock signal and producing first and second delay signals. The second delay signal has a delay time different from that of the first delay signal. The first delay signal controls flip-flop circuitry which receives a data signal and outputs a signal indicative of the data signal. The first delay signal also controls a first latch circuit to receive the signal from the flip-flop circuitry and output a signal with the delay time of the first delay signal. The second delay signal controls a second latch circuit to receive the signal from the flip-flop circuitry and output a signal with the delay time of the second delay signal. The signals output from the first and second latch circuits are logically combined by logic circuitry. The logic circuitry is either AND or OR circuitry. The logic circuitry outputs the result of the combination to driving circuitry which provides the current to drive the light emitting element in accordance with the output of the logic circuitry.
摘要翻译： 一种用于驱动用于高速光通信的发光元件的半导体器件。 半导体器件包括用于延迟时钟信号并产生第一和第二延迟信号的电路。 第二延迟信号具有与第一延迟信号不同的延迟时间。 第一延迟信号控制接收数据信号并输出指示数据信号的信号的触发器电路。 第一延迟信号还控制第一锁存电路以接收来自触发器电路的信号并输出具有第一延迟信号的延迟时间的信号。 第二延迟信号控制第二锁存电路以接收来自触发器电路的信号，并输出具有第二延迟信号的延迟时间的信号。 从第一和第二锁存电路输出的信号由逻辑电路逻辑组合。 逻辑电路是AND或OR电路。 逻辑电路将组合的结果输出到根据逻辑电路的输出提供电流驱动发光元件的驱动电路。
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公开(公告)号：EP0464524A1
公开(公告)日：1992-01-08
申请号：EP91110273.9
申请日：1991-06-21
IPC分类号： H03K19/094 , H03K19/003
CPC分类号： H03K19/09436 , H03K3/356034 , H03K19/00361 , H03K19/01707
摘要： A current-switching type compound semiconductor logic circuit which is high in an operating speed and low in power consumption. Voltage stabilizing transistors (25,26) are provided to the logic circuit so that voltage signal which are in-phase with the gates of driving transistors (21,22) and has a mean electric potential higher than that of the same by a predetermined value is applied to the gate thereof. The voltage stabilizing transistors (25,26) act as a buffer to prevent electric potential of the driving transistors (21,22) from fluctuating. As a result, it is possible to secure stable outputs in which the distortion of a waveform or the fluctuation of a cross point due to a jitter is hardly generated.
摘要翻译： 电流开关型复合半导体逻辑电路，其工作速度高，功耗低。 电压稳定晶体管（25,26）被提供给逻辑电路，使得电压信号与驱动晶体管（21,22）的栅极同相并且具有高于预定值的平均电位 被施加到其门。 稳压晶体管（25,26）充当缓冲器，以防止驱动晶体管（21,22）的电位波动。 结果，可以确保稳定的输出，其中几乎不产生波形失真或由于抖动引起的交叉点的波动。
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