公开(公告)号：EP1407393A4

公开(公告)日：2009-04-29

申请号：EP02752076

申请日：2002-06-21

申请人： CADENCE DESIGN SYSTEMS INC

发明人： WADLAND KEN ,  KINGSBURY GLENDINE

IPC分类号： G06F17/50 ,  H01L23/12

CPC分类号： G06F17/5077 ,  G06F2217/40

摘要： An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide singular ideal IC package routing solution. Topological Global Routing provides a mathematical abstraction of the problem that allows multiple optimizations to be performed prior to detailed routing. Preliminary disregard of electrical routing segment width and required clearance allows the global topological solution to be determined quickly. The global topological solution is used in conjunction with necessary design parameters to determine the optimal geometric routing solution. Guide points are determined using the geometric routing solution. A detail router uses the guide points as corners when performing the actual routing.

公开(公告)号：EP2051176A1

公开(公告)日：2009-04-22

申请号：EP08252875.3

申请日：2008-08-29

申请人： Cadence Design Systems, Inc.

发明人： Liu, Hongzhou ,  Hui, Zhang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： Techniques are presented for improving parametric yield. As part of an automatic sizing process for a circuit, one set of techniques receives a target value for a performance goal and then optimizes, with respect to the number of standard deviations, the distance by which the mean value of a distribution of the performance goal differs from the target value. In a second set of techniques, as part of an automatic sizing process during a circuit design process, the operation of the circuit is simulated to determine the distribution of a performance goal for a first design point. It is then determined whether a second design point is sufficiently close to the first design point and, if so, the simulation for the first design point is used for evaluating the second design point in an optimization process.

摘要翻译： 提出了提高参数产量的技术。 作为电路的自动调整过程的一部分，一组技术接收目标值作为性能目标，然后相对于标准偏差的数量来优化性能目标的分布的平均值的距离 与目标值不同。 在第二组技术中，作为电路设计过程中的自动调整过程的一部分，模拟电路的操作以确定第一设计点的性能目标的分布。 然后确定第二设计点是否足够靠近第一设计点，如果是，则在优化过程中使用第一设计点的模拟来评估第二设计点。

公开(公告)号：EP1923804A2

公开(公告)日：2008-05-21

申请号：EP07022315.1

申请日：2007-11-16

申请人： Cadence Design Systems, Inc.

发明人： Dengi, Enis Aykut ,  Ling, Feng ,  Song, Ben ,  Harris, Warren

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A system and method for modeling an IC (integrated circuit) employs a mesh model and a grid model for separating impedance effects between nearby and far-away pairs of mesh elements. Models for relating currents and voltages can be incrementally adapted from other designs or design elements in applications including mixed-signal, analog and RF (radio frequency) circuits.

摘要翻译： 用于对IC（集成电路）进行建模的系统和方法使用网格模型和网格模型来分离近距离和远距离的网格元素对之间的阻抗效应。 用于相关电流和电压的模型可以在包括混合信号，模拟和RF（射频）电路的应用中的其他设计或设计元件中逐渐适应。

公开(公告)号：EP1763805A4

公开(公告)日：2007-12-12

申请号：EP05771286

申请日：2005-06-04

申请人： CADENCE DESIGN SYSTEMS INC

发明人： HETZEL ASMUS ,  MALHOTRA ANISH ,  FUJIMURA AKIRA ,  JACQUES ETIENNE ,  FRANKLE JON ,  HARRISON DAVID S ,  FEATHER HEATH ,  MATVEEV ALEXANDRE ,  KING ROGER

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools. An LPD wiring model allows at least one wiring layer (200) to have a set of regions (205, 210, 215) that each has a different preferred direction (-45°, 0°, 90°) than the particular wiring layer. In addition, each region (205, 210, 215) has a local preferred direction (-45°, 0°, 90°) that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set. Some embodiments also provide a Graphical User Interface (GUI) that facilitates a visual presentation of an LPD design layout and provides tools to create and manipulate LPD regions in a design layout.

摘要翻译： 本发明的一些实施例提供与一个或多个EDA工具一起使用的本地优选方向（LPD）布线模型。 LPD布线模型允许至少一个布线层（200）具有一组区域（205,210,215），每个区域具有与特定布线层不同的优选方向（-45°，0°，90°）。 另外，每个区域（205,210,215）具有不同于该组中至少一个其他区域的局部优选方向的局部优选方向（-45°，0°，90°）。 此外，至少两个区域具有两个不同的多边形形状，并且该组中的任何区域都不包含该组中的另一个区域。 一些实施例还提供便于LPD设计布局的视觉呈现的图形用户界面（GUI），并提供用于在设计布局中创建和操纵LPD区域的工具。

公开(公告)号：EP1402401A4

公开(公告)日：2007-10-03

申请号：EP02742137

申请日：2002-06-17

申请人： CADENCE DESIGN SYSTEMS INC ,  SALUJA SANJEEV

发明人： SALUJA SANJEEV ,  MATHUR ANMOL

IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F17/50 ,  G06F17/10

CPC分类号： G06F8/443 ,  G06F9/44 ,  G06F17/5045

摘要： A Huffman algorithm is applied to revise the topology of a data flow graph. The result of the application of the algorithm is an increase in the sizes of at least some of the clusters through enhanced mergeability. The Huffman rebalancing of the topology may also result in the benefit of allowing further pruning of the bitwidths of data flow paths, which may further enhance mergeability.

公开(公告)号：EP1759322A2

公开(公告)日：2007-03-07

申请号：EP05740554.0

申请日：2005-04-29

申请人： Cadence Design Systems, Inc.

发明人： SCHEFFER, Louis, K. ,  TEIG, Steven

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： A method for modifying an IC layout using a library of pretabulated models, each model containing an environment with a feature, one or more geometries, and a modification to the feature that is calculated to produce a satisfactory feature on a wafer. The model may also contain a simulation of the environment reflecting no processing variations and/or a re-simulation of the environment reflecting one or more processing variations. The model may also contain data describing an electrical characteristic of the environment as a function of one or more process variations and/or data describing an adjustment equation that uses geometry coverage percentages of particular areas in the layout to determine an adjustment to the modification. In some embodiments, an upper layout for an upper of an IC are modified using information (such a density map) relating to a lower layout for a lower layer of the IC.

公开(公告)号：EP1756741A2

公开(公告)日：2007-02-28

申请号：EP05755944.5

申请日：2005-06-04

申请人： Cadence Design Systems, Inc.

发明人： HETZEL, Asmus ,  MALHOTRA, Anish ,  CHERUKURI, Deepak ,  JACQUES, Etienne ,  FRANKLE, Jon

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method for defining routes in a design layout with at least one particular wiring layer that has at least two regions (200, 300) with different local preferred wiring directions (210, 305). The method then uses the differing local preferred wiring directions (205, 215) to define a detailed route on the wiring layer. In some embodiments, the method defines a first route (210) that traverse first (200) and second regions (300) between two layers by using a first via that has a first pad in the second region.

公开(公告)号：EP1579274A4

公开(公告)日：2006-06-07

申请号：EP03764633

申请日：2003-07-14

申请人： CADENCE DESIGN SYSTEMS INC

发明人： PACK ROBERT C ,  SHEFFER LOUIS K

IPC分类号： G03F20060101 ,  G03F1/84 ,  G03F9/00 ,  G06F7/60 ,  G06F17/10 ,  G06F19/00 ,  G03F1/00

CPC分类号： G03F1/84

摘要： A method for inspecting lithography masks (108) includes generating integrated circuit design data (102) and using context information from the integrated circuit design data to inspect a mask.

公开(公告)号：EP1235164A3

公开(公告)日：2005-09-28

申请号：EP02251293.3

申请日：2002-02-25

申请人： Cadence Design Systems, Inc.

发明人： He, Limin ,  Yao, So-Zen ,  Deng, Wenyong ,  Chen, Jing ,  Chao, Liang-Jih

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

公开(公告)号：EP1266312A4

公开(公告)日：2004-12-29

申请号：EP01913222

申请日：2001-03-01

申请人： CADENCE DESIGN SYSTEMS INC

发明人： CHAO HAN-HSUN ,  RAZDAN RAHUL ,  SALDANHA ALEXANDER

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/504

摘要： A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, but can be a simplified gate level representation because the verification process is only concerned with the logical behavior, not the actual structure. This allows the simulation to execute more quickly. Since the conditions are only captured between register elements, it can be formally proved whether or not the path can be exercised. If no register value can activate the path, then the analysis is done. Otherwise, a simulation is performed to determine whether the register values required to active the condition actually occur. If the Boolean condition can be satisfied, the simulation is performed on the sequential logic to justify those values. If the satisfiability engine fails to finish, then the simulation is run on the combinational logic, and an attempt is made to justify the values sequentially as well.