公开(公告)号：EP2602824A4

公开(公告)日：2015-02-18

申请号：EP11814584

申请日：2011-07-29

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： MASUDA TAKEYOSHI

IPC分类号： H01L29/12 ,  H01L21/3065 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L21/0445 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0623 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8613 ,  Y10S438/931

公开(公告)号：EP2555246A4

公开(公告)日：2014-05-14

申请号：EP10848493

申请日：2010-12-17

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： HARADA SHIN ,  HIYOSHI TORU ,  WADA KEIJI ,  MASUDA TAKEYOSHI

IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L21/20 ,  H01L21/318 ,  H01L21/336 ,  H01L29/04 ,  H01L29/12 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/66068 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/049 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/518 ,  H01L29/7802 ,  H01L29/94

摘要： A semiconductor device (1) includes: a substrate (2) made of silicon carbide and having a main surface (2A) having an off angle of not less than -3° and not more than +5° relative to a (0-33-8) plane in a direction; a p type layer (4) made of silicon carbide and formed on the main surface (2A) of the substrate (2) by means of epitaxial growth; and an oxide film (8) formed in contact with a surface of the p type layer (4). A maximum value of nitrogen atom concentration is 1 × 10 21 cm -3 or greater in a region within 10 nm from an interface between the p type layer (4) and the oxide film (8).

公开(公告)号：EP2477213A4

公开(公告)日：2014-05-14

申请号：EP10815258

申请日：2010-08-24

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： HONAGA MISAKO ,  MASUDA TAKEYOSHI ,  HARADA SHIN

IPC分类号： H01L23/544 ,  H01L21/336 ,  H01L29/12 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L23/544 ,  H01L29/1608 ,  H01L29/66068 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device (1) includes the steps of forming a semiconductor layer made of SiC on an SiC substrate, forming a film on the semiconductor layer, and forming a groove (2) in the film. The semiconductor device (1) including a chip (10) having an interlayer insulating film includes a groove (2) formed in the interlayer insulating film to cross the chip (10).

公开(公告)号：EP2600402A4

公开(公告)日：2013-12-25

申请号：EP11812210

申请日：2011-06-29

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： HIYOSHI TORU ,  WADA KEIJI ,  MASUDA TAKEYOSHI ,  SHIOMI HIROMU

IPC分类号： H01L29/12 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L21/049 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802

摘要： A MOSFET (100) includes a silicon carbide substrate (1) including a main surface (1A) having an off angle of not less than 50° and not more than 65° with respect to a {0001} plane, a buffer layer (2) and a drift layer (3) formed on the main surface (1A), a gate oxide film (91) formed on and in contact with the drift layer (3), and a p type body region (4) of a p conductivity type formed in the drift layer (3) to include a region in contact with the gate oxide film (91). The p type body region (4) has a p type impurity density of not less than 5 × 10 16 cm -3

摘要翻译： 一种MOSFET（100）包括：碳化硅衬底（1），其包括相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面（1A），缓冲层 ）和形成在主表面（1A）上的漂移层（3），形成在漂移层（3）上并与其接触的栅极氧化物膜（91）以及形成p导电类型的p型体区（4） 在漂移层（3）中包括与栅极氧化物膜（91）接触的区域。 p型体区（4）具有不小于5×10 16 cm -3的p型杂质密度

公开(公告)号：EP2413364A4

公开(公告)日：2013-05-08

申请号：EP10756048

申请日：2010-03-23

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： WADA KEIJI ,  HARADA SHIN ,  MASUDA TAKEYOSHI ,  HONAGA MISAKO

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/04 ,  H01L29/16

CPC分类号： H01L29/94 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802

摘要： A MOSFET 1 includes: a silicon carbide (SiC) substrate (2) having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer (21) formed on the main surface of the SiC substrate (2); and an insulating film (26) formed in contact with a surface of the semiconductor layer (21). The MOSFET 1 has a sub-threshold slope of not more than 0.4 V/Decade.

公开(公告)号：EP2357671A4

公开(公告)日：2013-05-01

申请号：EP09827391

申请日：2009-02-03

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： HARADA SHIN ,  MASUDA TAKEYOSHI ,  WADA KEIJI ,  TSUMORI MASATO

IPC分类号： H01L29/78 ,  H01L21/316 ,  H01L21/336 ,  H01L29/12

CPC分类号： H01L29/1608 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/3003 ,  H01L21/324 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/94

公开(公告)号：EP2058848A4

公开(公告)日：2011-01-12

申请号：EP07807695

申请日：2007-09-21

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： MASUDA TAKEYOSHI ,  NAMIKAWA YASUO

IPC分类号： H01L21/337 ,  H01L29/417 ,  H01L29/808

CPC分类号： H01L29/808 ,  H01L21/048 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66901

公开(公告)号：EP2096669A4

公开(公告)日：2009-11-18

申请号：EP07792460

申请日：2007-08-13

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： FUJIKAWA KAZUHIRO ,  MASUDA TAKEYOSHI

IPC分类号： H01L21/324 ,  H01L21/265 ,  H01L21/337 ,  H01L29/808

CPC分类号： H01L29/808 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66901 ,  Y10S438/931

公开(公告)号：EP2897175A4

公开(公告)日：2016-06-01

申请号：EP13836475

申请日：2013-07-04

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： MASUDA TAKEYOSHI ,  SAITOH YU ,  HAYASHI HIDEKI ,  HIYOSHI TORU ,  WADA KEIJI

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/336 ,  H01L29/12

CPC分类号： H01L29/513 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7813

公开(公告)号：EP2897176A4

公开(公告)日：2016-05-18

申请号：EP13836826

申请日：2013-07-30

申请人： SUMITOMO ELECTRIC INDUSTRIES

发明人： SAITOH YU ,  MASUDA TAKEYOSHI ,  HAYASHI HIDEKI

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/336 ,  H01L29/12

CPC分类号： H01L29/66666 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827 ,  Y10S438/931

摘要： A trench (TR) having a side wall (SW) and a bottom portion (BT) is formed in a silicon carbide substrate (100). A trench insulating film (201A) is formed to cover the bottom portion (BT) and the side wall (SW). A silicon film (201 S) is formed to fill the trench with the trench insulating film (201 A) being interposed therebetween. The silicon film (201 S) is etched so as to leave a portion of the silicon film (201 S) that is disposed on the bottom portion (BT) with the trench insulating film (201A) being interposed therebetween. The trench insulating film (201A) is removed from the side wall (SW). By oxidizing the silicon film (201S), a bottom insulating film is formed. A side wall insulating film is formed on the side wall (SW).