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41.发明公开Apparatus and method for non-blocking execution on static scheduled processor 审中-公开装置和方法用于静态调度的处理器上无阻塞执行
公开(公告)号：EP2778906A1
公开(公告)日：2014-09-17
申请号：EP14158460.7
申请日：2014-03-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwon, Kwon Taek , Woo, Sang Oak , Lee, Shi Hwa , Jung, Seok Yoon
IPC: G06F9/38
CPC classification number: G06F9/3836 , G06F9/30043 , G06F9/3832 , G06F9/3842 , G06F9/3859
Abstract: An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor may include at least one functional unit (FU) to execute the at least one operation, and the at least one FU may process the transferred input data using at least one of a regular latency operation and an irregular latency operation.
Abstract translation: 为非阻塞一个静态调度处理器的执行，该设备包括处理器使用传输的输入数据进行处理的至少一个操作，并INPUTBUFFER用于将输入数据传送到所述处理器，并存储结果的装置和方法 处理所述至少一个操作，worin处理器可以包括至少一个功能单元（FU），以执行所述至少一个操作，并且所述至少一个FU可以使用常规延迟操作的至少一个处理该传输的输入数据和 以不规则的延时操作。
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公开(公告)号：EP2487589A1
公开(公告)日：2012-08-15
申请号：EP12000682.0
申请日：2007-12-18
Applicant: Intel Corporation (INTEL)
Inventor： Saha, Bratin , Adl-Tabatabai, Ali-Reza , Wang, Cheng , Wu, Youfeng , Chen, Wei-Yu
CPC classification number: G06F8/458 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863 , G06F9/467
Abstract: A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.
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43.发明公开RELIABLE EXECUTION USING COMPARE AND TRANSFER INSTRUCTION ON AN SMT MACHINE 审中-公开可靠地执行使用一个调解与转移指令上的贴片机
公开(公告)号：EP2425330A1
公开(公告)日：2012-03-07
申请号：EP10719678.4
申请日：2010-04-27
Applicant: Advanced Micro Devices, Inc.
Inventor： SUDHAKAR, Ranganathan , QUACH, Nhon, T.
CPC classification number: G06F9/3851 , G06F9/30189 , G06F9/3824 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3863 , G06F9/3891 , G06F11/1407 , G06F11/1497 , G06F11/1641 , G06F11/1683 , G06F2201/845
Abstract: A system and method for efficient reliable execution on a simultaneous multithreading machine. A processor is placed in a reliable execution mode (REM) to detect possible errors during execution of a software application. Only two threads may be configured to operate in this mode. Floating-point store and integer-transfer unary instructions may be converted to new instructions. Each new instruction has two source operands, each corresponding to a different thread is specified by a same logical register number as a single source operand of the original unary instruction. All other instructions are replicated, wherein the original instruction and its twin are assigned to different threads. Simultaneous multi-threaded (SMT) floating-point logic may only be able to provide lockstep execution when it communicates using the new instruction with instantiated integer independent clusters. The new instruction cannot begin until both source operands are ready, which are subsequently compared to determine any mismatches or errors.
Abstract translation: 一种用于在同步多线程机器上高效可靠地执行系统和方法。 处理器被以可靠的执行模式（SEM）的软件应用的执行期间检测到可能的错误放置。 只有两个线程可以被配置成这种方式进行操作。 浮点和整数店内传递一元指令可以被转换为新的指令。 每一个新的指令有两个源操作数，每个对应于一个不同的线程被乘以相同的逻辑寄存器号码作为原始指令的一元的单源操作数指定。 其他所有的指令都被复制，worin原始指令和它的孪生兄弟被分配到不同的线程。 同时多线程（SMT）浮点逻辑可能仅能够在其传送使用具有实例化的整数独立簇的新的指令，以提供锁步执行。 新指令不能开始，直到两个源操作数都准备好了，随后将其比较确定的矿山任何不匹配或错误。
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公开(公告)号：EP0992904B1
公开(公告)日：2010-06-09
申请号：EP99400552.8
申请日：1999-03-08
Applicant: TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
Inventor： Deao, Douglas E. , Buser, Mark.L , Nidegger, Frederick , Russell, David
IPC: G06F11/36
Abstract: A processor core (102) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A cache (814) located within a megacell on a single integrated circuit (800) is provided to reduce instruction access time. The cache is for instructions only so that cache coherency measures due to writing data are not needed. Cache coherence circuitry (816) is included within the megacell and monitors selected signals to maintain coherence within the cache during emulation and debugging operations.
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公开(公告)号：EP1122638B1
公开(公告)日：2004-09-15
申请号：EP01110865.1
申请日：1992-06-22
Applicant: Hitachi, Ltd. , Hitachi ULSI Systems Co.,Ltd.
Inventor： Fukada, Kaoru Semiconductor & I.Circuits , Yamazaki, Takanaga Semiconductor & I.Circuits , Akao, Yasushi Hitachi, Ltd., Intel. Prop. Group , Baba, Shiro Hitachi, Ltd., Intel. Prop. Group , Kihara, Toshimasa Semiconductor & I.Circuits , Kurakazu, Keiichi Semiconductor & I.Circuits , Tawara, Yasuhiro Semiconductor & I.Circuits , Kashiwagi, Yugo Semiconductor & I.Circuits , Fujita, Shuya Semiconductor & I.Circuits , Ishida, Katsuhiko Semiconductor & I.Circuits , Chaki, Hideaki Semiconductor & I.Circuits , Sugawara, Tadahiko Hitachi,Ltd. Intel. Prop.Group , Kainaga, Masahiro Semiconductor & I.Circuits , Noguchi, Koki Semiconductor & I.Circuits , Kawasaki, Shumpei Semiconductor & I.Circuits , Sakakibara, Eiji Hitachi Ltd., Intel. Prop.Group , Tsukamoto, Takashi Hitachi Ulsi Systems Co, , Masumura, Shigeki Hitachi Ulsi Systems Co, , Sawa, Noriko Hitachi Ltd., Intel. Prop. Group , Asano, Yoichi Hitachi Ltd., Intel. Prop. Group , Watabe, Mitsuru Hitachi Ltd., Intel. Prop. Group
CPC classification number: G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
Abstract: RISC-type microprocessor has a fixed struction lenght of 2 bits, whilst the data use size is 2 bits,where m is greater than or equal to n.
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Patent Agency Ranking46.发明公开Decoupled architecture processor with loop pipeline 有权Entkoppelte Prozessorarchitektur mit Schleifen-Pipeline
公开(公告)号：EP1406165A2
公开(公告)日：2004-04-07
申请号：EP03029611.5
申请日：1998-09-04
Applicant: Infineon Technologies North America Corp.
Inventor： Fleck, Rod G. , Baror, Gigy , Moeller, Ole H.
IPC: G06F9/38
CPC classification number: G06F9/3891 , G06F9/3013 , G06F9/30141 , G06F9/381 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3889
Abstract: The present invention relates to a data processor which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions a third pipeline for executing loop instructions, a unit for issuing multiple instructions to said pipelines, a first set of registers being coupled with said first pipeline, and a second set of registers being coupled with said second pipeline and said third pipeline, wherein first second and third pipelines process data in parallel.
Abstract translation: 有两条管道，一条用于数据指令，另一条用于地址指令。 一个单元向管道发出多个指令。 两组寄存器分别连接到管道。 管道并行处理数据。
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公开(公告)号：EP0992904A3
公开(公告)日：2003-01-22
申请号：EP99400552.8
申请日：1999-03-08
Applicant: TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
Inventor： Deao, Douglas E. , Buser, Mark.L , Nidegger, Frederick , Russell, David
IPC: G06F11/36
Abstract: A processor core (102) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A cache (814) located within a megacell on a single integrated circuit (800) is provided to reduce instruction access time. The cache is for instructions only so that cache coherency measures due to writing data are not needed. Cache coherence circuitry (816) is included within the megacell and monitors selected signals to maintain coherence within the cache during emulation and debugging operations.
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公开(公告)号：EP1122638A3
公开(公告)日：2002-01-23
申请号：EP01110865.1
申请日：1992-06-22
Applicant: Hitachi, Ltd. , Hitachi ULSI Systems Co.,Ltd.
Inventor： Fukada, Kaoru Semiconductor & I.Circuits , Yamazaki, Takanaga Semiconductor & I.Circuits , Akao, Yasushi Hitachi, Ltd., Intel. Prop. Group , Baba, Shiro Hitachi, Ltd., Intel. Prop. Group , Kihara, Toshimasa Semiconductor & I.Circuits , Kurakazu, Keiichi Semiconductor & I.Circuits , Tawara, Yasuhiro Semiconductor & I.Circuits , Kashiwagi, Yugo Semiconductor & I.Circuits , Fujita, Shuya Semiconductor & I.Circuits , Ishida, Katsuhiko Semiconductor & I.Circuits , Chaki, Hideaki Semiconductor & I.Circuits , Sugawara, Tadahiko Hitachi,Ltd. Intel. Prop.Group , Kainaga, Masahiro Semiconductor & I.Circuits , Noguchi, Koki Semiconductor & I.Circuits , Kawasaki, Shumpei Semiconductor & I.Circuits , Sakakibara, Eiji Hitachi Ltd., Intel. Prop.Group , Tsukamoto, Takashi Hitachi Ulsi Systems Co, , Masumura, Shigeki Hitachi Ulsi Systems Co, , Sawa, Noriko Hitachi Ltd., Intel. Prop. Group , Asano, Yoichi Hitachi Ltd., Intel. Prop. Group , Watabe, Mitsuro Hitachi Ltd., Intel. Prop. Group
CPC classification number: G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction de-coding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.
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公开(公告)号：EP1122638A2
公开(公告)日：2001-08-08
申请号：EP01110865.1
申请日：1992-06-22
Applicant: Hitachi, Ltd. , Hitachi ULSI Systems Co.,Ltd.
Inventor： Fukada, Kaoru Semiconductor & I.Circuits , Yamazaki, Takanaga Semiconductor & I.Circuits , Akao, Yasushi Semiconductor & I.Circuits , Baba, Shiro Semiconductor & I.Circuits , Kihara, Toshimasa Semiconductor & I.Circuits , Kurakazu, Keiichi Semiconductor & I.Circuits , Tawara, Yasuhiro Semiconductor & I.Circuits , Kashiwagi, Yugo Semiconductor & I.Circuits , Fujita, Shuya Semiconductor & I.Circuits , Ishida, Katsuhiko Semiconductor & I.Circuits , Chaki, Hideaki Semiconductor & I.Circuits , Sugawara, Tadahiko Semiconductor & I.Circuits , Kainaga, Masahiro Semiconductor & I.Circuits , Noguchi, Koki Semiconductor & I.Circuits , Kawasaki, Shumpei Semiconductor & I.Circuits , Sakakibara, Eiji Semiconductor & I.Circuits , Tuskamoto, Takashi Semiconductor & I.Circuits , Masumura, Shigeki Semiconductor & I.Circuits , Sawa, Noriko Semiconductor & I.Circuits , Asano, Yoichi Semiconductor & I.Circuits , Watabe, Mitsuru Semiconductor & I.Circuits
CPC classification number: G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction de-coding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.
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公开(公告)号：EP0992904A2
公开(公告)日：2000-04-12
申请号：EP99400552.8
申请日：1999-03-08
Applicant: TEXAS INSTRUMENTS INC. , TEXAS INSTRUMENTS FRANCE
Inventor： Deao, Douglas E. , Buser, Mark.L , Nidegger, Frederick , Russell, David
IPC: G06F11/00
Abstract: A processor core (102) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A cache (814) located within a megacell on a single integrated circuit (800) is provided to reduce instruction access time. The cache is for instructions only so that cache coherency measures due to writing data are not needed. Cache coherence circuitry (816) is included within the megacell and monitors selected signals to maintain coherence within the cache during emulation and debugging operations.
Abstract translation: 提供了一种处理器核心（102），其是具有可变指令长度的可编程数字信号处理器（DSP），提供高代码密度和易编程。 架构和指令集针对低功耗和高效率执行DSP算法（如无线电话）以及纯控制任务进行了优化。 提供位于单个集成电路（800）上的兆位内的高速缓存（814）以减少指令访问时间。 高速缓存仅用于指令，因此不需要由于写入数据而进行高速缓存一致性测量。 高速缓存一致性电路（816）被包括在巨型电平内，并且在仿真和调试操作期间监视所选择的信号以保持高速缓存内的一致性。
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