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公开(公告)号：EP0767589A3
公开(公告)日：1999-07-07
申请号：EP96304876.4
申请日：1996-07-02
发明人： Kim, Young-Chul
IPC分类号： H04N9/45
CPC分类号： H04N9/45
摘要： A clock signal generator construction. The generator comprises synchronizing separation means for separating a horizontal synchronizing signal from an input composite video signal; burst separation means for separating a color burst signal from the input composite video signal; phase error detection means for receiving the horizontal synchronizing signal, detecting a phase error and outputting a phase error signal for a previous horizontal period; phase change detection means for receiving the color burst signal, detecting a phase change of the color burst signal, and outputting a phase change signal for a present horizontal period; adding means for adding the phase error signal and the phase change signal; and clock signal generation means for receiving an output of the adding means and generating a clock signal which is synchronized with the input composite video signal.
摘要翻译： 时钟信号发生器构造。 发生器包括同步分离装置，用于从输入的复合视频信号中分离水平同步信号; 脉冲串分离装置，用于从输入的复合视频信号中分离色同步信号; 相位误差检测装置，用于接收水平同步信号，检测相位误差并输出前一水平周期的相位误差信号; 相变检测装置，用于接收色同步信号，检测色同步信号的相位变化，并输出当前水平周期的相位变化信号; 用于添加相位误差信号和相位变化信号的加法装置; 以及时钟信号发生装置，用于接收加法装置的输出并产生与输入的复合视频信号同步的时钟信号。
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公开(公告)号：EP0906701A1
公开(公告)日：1999-04-07
申请号：EP98904328.0
申请日：1998-03-05
发明人： WISSING, Roy, Wilhelmus, Bernardus , VAN LAMMEREN, Johannes, Petrus, Maria , PELGROM, Marcellinus, Johannes, Maria
摘要： In a method of demodulating an analog chrominance signal (C), digital quadrature signals are generated (DPA, SIN ROM, COS ROM) for demodulating (MUL DAC U, MUL DAC V) the analog chrominance signal (C) to obtain analog demodulated color difference signals (U, V). A digital phase error signal is furnished (ΣΔ mod) from at least one (V) of the analog demodulated color difference signals (U, V). The digital phase error signal is digitally filtered (DLF) to obtain a phase control signal (K) for the digital quadrature signals generation (DPA, SIN ROM, COS ROM).
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43.发明公开
公开(公告)号：EP0855802A2
公开(公告)日：1998-07-29
申请号：EP98300353.4
申请日：1998-01-19
发明人： Kiyose, Masashi , Ito, Hiroya
CPC分类号： H03L7/0997 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/10 , H03L7/107 , H04N9/45 , H04N11/146
摘要： A PLL circuit which outputs an oscillation clock signal synchronous with a reference clock includes a phase lock detector for detecting if the oscillation clock signal is synchronous with the reference clock. If the phase lock detector detects a phase difference between the oscillation clock signal and the reference clock, a charge pump circuit is used to alter the oscillation clock signal so that the oscillation signal is placed back in sync with the reference clock. The charge pump selects one of a ground potential and a power supply potential in response to a comparison result of the oscillation clock signal and the reference clock. The charge pump pulls a constant current to ground from an output terminal of the charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential is selected, thereby producing an output which alternately repeats the ground potential and the power supply potential.
摘要翻译： 输出与参考时钟同步的振荡时钟信号的PLL电路包括用于检测振荡时钟信号是否与参考时钟同步的锁相检测器。 如果锁相检测器检测到振荡时钟信号和参考时钟之间的相位差，则使用电荷泵电路来改变振荡时钟信号，使振荡信号与参考时钟同步。 响应于振荡时钟信号和参考时钟的比较结果，电荷泵选择接地电位和电源电位之一。 当选择接地电位时，电荷泵从电荷泵电路的输出端引出恒定的电流，并在选择电源电位时向电荷泵电路的输出端提供恒定电流，从而产生输出 其交替地重复地电位和电源电位。
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公开(公告)号：EP0716550A3
公开(公告)日：1997-06-11
申请号：EP95308459.7
申请日：1995-11-24
发明人： Williams, Gareth R.
IPC分类号： H04N9/45
CPC分类号： H04N9/45
摘要： An arrangement for synchronizing a digitally generated colour subcarrier signal to the colour burst signal from another video signal, such as that from a video casette recorder or from a cable television signal, in a manner that allows a line locked clock to be used without causing unacceptable disturbance to the generated subcarrier signal.
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公开(公告)号：EP0550420A3
公开(公告)日：1993-08-18
申请号：EP93200689.3
申请日：1988-03-28
IPC分类号： H04N5/12
摘要： A digital TV receiver includes an apparatus for generating a skew corrected clock. The apparatus consists of a fixed frequency, free running oscillator (22) for producing a signal (FFOS) having a frequency which is a fixed integer multiple K of the desired nominal frequency of the skew-corrected clock signal, and a divide-by-K circuit (30) which is reset once every horizontal line. The divide-by-K circuit comprises a divide-by-m circuit connected in series with a flip-flop (50), with said divide-by-m circuit (40) being reset by a first control signal (FCS) once every horizontal line. The apparatus additionally includes means (Fig. 2/SCS) for preventing the output of the flip-flop (50) from changing while the divide-by-m circuit is reset in response to the first control signal (FCS). In accordance with another aspect of this invention, the state of the divide-by-K circuit (30) is captured (150/SES) and saved for use in a chroma demodulation apparatus (Fig. 6) just before it is reset.
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46.发明公开DUAL MODE GEN-LOCK SYSTEM WHICH AUTOMATICALLY LOCKS TO COLOR BURST OR TO SYNC INFORMATION 失效双操作同步器钥匙系统具有自动司法化爆裂或同步信息。
公开(公告)号：EP0400021A1
公开(公告)日：1990-12-05
申请号：EP89901160.0
申请日：1988-12-27
CPC分类号： H04N9/45
摘要： Le système décrit génère des impulsions de synchronisation à haute fréquence qui sont automatiquement synchronisées sur un signal vidéo externe. Lors de la présence d'une salve de référence dans le signal vidéo externe, les impulsions de synchronisation sont synchronisées sur ladite salve. Cependant en l'absence de cette salve de référence, les impulsions de synchronisation sont synchronisées sur les impulsions de synchronisation horizontale du signal vidéo externe. Cette opération s'effectue grâce à la présence d'une boucle à verrouillage de phase qui comporte un oscillateur marchant librement à la fréquence de base désirée, ainsi qu'un détecteur de phase pour comparer la différence de phase entre une portion sélectionnée du signal de référence de la boucle à verrouillage de phase et une portion sélectionnée de soit la salve de référence soit les impulsions de synchronisation horizontale.
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公开(公告)号：EP0247891A3
公开(公告)日：1989-07-05
申请号：EP87304767.4
申请日：1987-05-29
发明人： Balaban, Alvin Reuben , Demmer, Walter Heinrich , Patel, Chandrakant Bhailalbhai , Harwood, Leopold Albert
摘要： A phase locked loop is provided, which may be used in digital systems having clock signal frequency instabilities. The PLL has an analog oscillator (342) the frequency of which is determined by an analog control signal. The oscillatory signal is digitised (344) and phase-compared (338) with a digital reference signal, the digital output of the phase comparator being converted (340) to an analog signal to provide the oscillator control signal. In an application of the invention to a digital television receiver having a line-locked clock, the phase locked loop (350) regenerates two quadrature phase related subcarrier signals (COS,SIN) that are used to synchronously demodulate the chrominance signal components (CB) of the composite video signals into two color information signals (I,Q). The analog voltage-controlled oscillator (342) of the phase locked loop (350) generates a signal that is independent of any frequency instability in the line-locked clock signal. The analog-to-digital converter (344) digitizes this signal to provide one of the subcarrier signals, from which is generated the quadrature subcarrier signal, for example from a read-only memory (348). The two color information signals (I,Q) are obtained by multiplying (332,334) the chrominance signals by the first and second subcarrier signals. The phase comparator (336) determines the phase of the vector sum of the two color information signals and compares this against a desired phase value to generate a phase difference signal. The phase difference signal is filtered (338) and applied to the digital-to-analog converter (340) whichprovides the frequency control signal for the analog oscillator (342). A tracking filter (346) may be inserted at the output port of the analog-to-digital converter (344) to allow its quantization resolution to be reduced without affecting the performance of the phase locked loop.
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48.发明授权
公开(公告)号：EP0078045B1
公开(公告)日：1988-08-10
申请号：EP82109844.9
申请日：1982-10-25
申请人： Hitachi, Ltd.
发明人： Aizawa, Iwao , Masuda, Michio
IPC分类号： H04N5/06
CPC分类号： H04N9/45 , H04N5/3765
摘要： A synchronizing signal generating circuit generating a horizontal synchronizing signal applied to a solid-state color video camera comprises an oscillator generating an oscillation output signal having a frequency which is n (n: an integer) times as high as the horizontal frequency, a frequency divider dividing the frequency of the oscillation output signal from the oscillator to generate a pulse signal having a recurrence frequency equal to the horizontal frequency, and another oscillator generating, in response to the application of the pulse signal to its control terminal, a horizontal clock pulse signal whose oscillation phase is controlled to be maintained at the same fixed phase in each horizontal period.
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公开(公告)号：EP0175434A2
公开(公告)日：1986-03-26
申请号：EP85302663.1
申请日：1985-04-16
申请人： AMPEX CORPORATION
发明人： Luke, Rylan D.
IPC分类号： H04N9/45
CPC分类号： H04N9/45
摘要： A signal generator for generating a clocked PAL reference video signal from a single signal source. A counter-divider (30) extracts subcarrier frequency component from the PAL reference video signal and a frequency changer (34) in combination with a counter-divider (38) extracts a horizontal frequency component from the PAL reference video signal.
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