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公开(公告)号：EP0886815A4
公开(公告)日：2001-10-04
申请号：EP96903403
申请日：1996-01-11
申请人： MICROPLANET LTD
IPC分类号： G05F1/613 , H02M1/00 , H02M1/42 , H02M5/293 , G05F1/40 , G05F1/44 , G05F1/56 , G05F1/618 , G05F3/16
CPC分类号： H02M1/4208 , G05F1/613 , H02M5/293 , Y02B70/126
摘要： The method and apparatus of the invention involve electronic power control by varying the amplitude of an electrical power supply voltage or current. A power controller is disclosed for controlling an AC input voltage to a load, the input voltage having one or more phases. The controller circuit has four independently controllable switches (Q1, Q2, Q3, Q4) and at least one inductor (L1), one such circuit for each input line to be regulated, the switches and inductor(s) of the circuit arranged in a conventional power regulator topology, whereby a selected regulator topology may be implemented, depending upon the position of the inductor(s) with respect to the input voltage. The controller has logic control with a two output polarity detector (160) in parallel with the input voltage, and a duty cycle modulator with two outputs; each of the outputs of the polarity detector and of duty modulator being inverted with respect to one another. Each switch is separately controlled and modulated by the logic control so that some combination of one or more of the switches is always electrically conducting.
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公开(公告)号：EP1125180A1
公开(公告)日：2001-08-22
申请号：EP00959542.2
申请日：2000-08-29
发明人： SESSIONS, D. C.
IPC分类号： G05F3/16
CPC分类号： G05F3/262
摘要： A high differential impedance load device (200a). In one embodiment, the present invention recites a load device (200a) including a first lead (202), a second lead (204), a first current mirror (210), a second current mirror (220), and a third lead (206). First lead (202), second lead (204), and third lead (206) are coupled to first current mirror (210) and second current mirror (220) such that a current sunk on first lead is approximately equal to a current sunk on second lead (204). Third lead (206) represents a reference voltage which is ground.
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43.发明公开Reference voltage generation circuit providing a stable output voltage 有权Bezugsspannungs发电机稳定器Ausgangs-Spannung
公开(公告)号：EP0945774A1
公开(公告)日：1999-09-29
申请号：EP99106053.4
申请日：1999-03-25
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G05F3/16
摘要： A reference voltage generation circuit includes a first current mirror (CM1) including first through third transistors (P1, P2, P3) with the second transistor (P2) on a reference side thereof, a second current mirror (CM4) including fourth and fifth transistors (N1, N2) connected in series with the first and the second transistors (P1, P2), respectively, and a voltage control block (Vsd1, Vsd2) for controlling the source-drain voltages the transistors (P1, P3) on the output side of the first current mirror (CM1). The voltage control block includes a first control block (Vsd1) having a configuration similar to the first current mirror (CM1), and a second control block (Vsd2) having a configuration similar to the second current mirror (CM4), both of which are connected between the first current mirror (CM1) and the second current mirror (CM2), with corresponding transistors connected in series. A stable output voltage can be obtained irrespective of variations in the potential of the voltage source (Vdd) for the reference voltage generation circuit.
摘要翻译： 参考电压产生电路包括第一电流镜（CM1），其第一至第三晶体管（P1，P2，P3）与其参考侧上的第二晶体管（P2）相连，第二电流镜（CM4）包括第四和第五晶体管 分别与第一和第二晶体管（P1，P2）串联连接的电压控制块（N1，N2）和用于控制源极 - 漏极电压的电压控制块（Vsd1，Vsd2）输出的晶体管（P1，P3） 侧的第一电流镜（CM1）。 电压控制块包括具有类似于第一电流镜（CM1）的配置的第一控制块（Vsd1）和具有类似于第二电流镜（CM4）的配置的第二控制块（Vsd2），它们都是 连接在第一电流镜（CM1）和第二电流镜（CM2）之间，其中相应的晶体管串联连接。 可以获得稳定的输出电压，而不管参考电压产生电路的电压源的电位（Vdd）的变化如何。
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公开(公告)号：EP0523893B1
公开(公告)日：1998-05-20
申请号：EP92306188.1
申请日：1992-07-06
发明人： Robinson, Barry J.
IPC分类号： H03K19/173 , H03K19/00 , G05F3/16
CPC分类号： G05F3/265 , H03K19/086
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公开(公告)号：EP0794477A1
公开(公告)日：1997-09-10
申请号：EP97106656.8
申请日：1994-07-04
发明人： Dutt, Saibul , Mohan, Muni
摘要： A circuit is provided for generating reference voltages which are at constant values (V p ) with respect to a varying DC voltage (V DC ). A fixed reference voltage (V BG ) is generated which is fixed with respect to the ground voltage (V SS ). Fractions (Vi) of this fixed reference voltage are added and subtracted to the varying DC voltage ( VDC ) by means of differential amplifiers (A3;A4), in order to produce the desired reference voltages respective to the varying DC voltage (V DC ).
摘要翻译： 提供电路，用于产生相对于变化的直流电压（VDC）处于恒定值（Vp）的参考电压。 产生相对于接地电压（VSS）固定的固定参考电压（VBG）。 通过差分放大器（A3; A4）将该固定参考电压的分数（Vi）相加并减去变化的直流电压（VDC），以产生相应于变化的直流电压（VDC）的所需参考电压。
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46.发明公开
公开(公告)号：EP0747713A2
公开(公告)日：1996-12-11
申请号：EP96108434.0
申请日：1996-05-28
CPC分类号： G05F3/24 , G01R1/203 , G01R19/0092 , H03K17/145 , H03K2217/0027
摘要： Ausgehend von dem bekannten Prinzip des "Sense"-FET wird zwischen dem Meßausgang und einem an Masse liegenden Meßwiderstand (5) ein steuerbarer Widerstand (6) angeschlossen. Sein Widerstandswert wird immer so eingestellt, daß die Drain-Sourcespannungen von Leistungs-FET einander (1)und "Sense"-FET (2) gleich sind. Damit wird erreicht, daß der Meßstrom dem Laststrom unabhängig von der Größe der Last proportional ist.
摘要翻译： 该电路具有额外的FET来感测功率FET的负载电流。 功率FET具有连接到电源的漏极和连接到负载的源极。 两个FET的漏极和栅极端子并联连接。 对应于负载电流除法的电流流过附加FET。 一个可控电阻连接在电流感应FET的源极之间。 一个MOSFET器件，并接地。 电阻值被设定为使得功率FET和感测FET的漏 - 源电压相等。 因此，测量电流与负载电流成正比，与负载的大小无关。 测量电阻可以由多晶硅制成，也可以是温度补偿电阻。
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47.发明公开Termination circuit in an ECL array of a row bias generator 失效Abschlussschaltung eines Eiem ECL-Array中的Reihen-Vorspannungsgenerators。
公开(公告)号：EP0523893A2
公开(公告)日：1993-01-20
申请号：EP92306188.1
申请日：1992-07-06
发明人： Robinson, Barry J.
IPC分类号： H03K19/173 , H03K19/00 , G05F3/16
CPC分类号： G05F3/265 , H03K19/086
摘要： A low voltage current mirror termination circuit used with an ECL gate array for providing a constant output emitter follower reference current (Ief) which is independent of voltage variations in a separate output emitter follower power supply source (VEF) includes a lateral PNP transistor (Qp), an NPN mirror transistor (Qx), at least one pull-down transistor (Qf), and at least one NPN output emitter follower transistor (Qo). The current through the collector of the lateral PNP transistor (Qp) defines a mirror current (Ip). The base of the lateral transistor (Qp) is connected to receive a base bias voltage VEP. The current through the collector of the pull-down transistor (Qf) defines the constant output emitter follower reference current (lef) which is proportional to the mirror current (Ip). The separate emitter follower power supply source (VEF) has a voltage which is lower than a supply source (VEE) so as to reduce significantly the power consumption.
摘要翻译： 与用于提供恒定输出射极跟随器参考电流（Ief）的ECL门阵列一起使用的低电压电流镜终端电路与独立的输出射极跟随器电源（VEF）中的电压变化无关，包括横向PNP晶体管（Qp ），NPN反射镜晶体管（Qx），至少一个下拉晶体管（Qf）和至少一个NPN输出射极跟随器晶体管（Qo）。 通过横向PNP晶体管（Qp）的集电极的电流定义了反射镜电流（Ip）。 横向晶体管（Qp）的基极被连接以接收基极偏置电压VEP。 通过下拉晶体管（Qf）的集电极的电流定义与镜电流（Ip）成比例的恒定输出射极跟随器参考电流（Ief）。 独立的射极跟随器电源（VEF）具有低于电源（VEE）的电压，从而显着降低功耗。
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公开(公告)号：EP0296193B1
公开(公告)日：1992-11-19
申请号：EP88900310.9
申请日：1987-11-30
发明人： DUNN, William, C.
IPC分类号： H03K19/0175 , H03K17/687 , H03K19/094 , G05F3/16
CPC分类号： H03K19/018521 , H03K19/00384 , H03K19/0948
摘要： A TTL compatible CMOS input circuit comprising a series of current mirror circuits (A, B, C) arranged so that the input transistor (Q4) is used to discharge the capacitive load (34) and one of a pair of transistors (Q4) in one of the mirror circuits (C) provides charging current for the load (34). Only one of the charging (Q3) and discharging (Q4) transistor switches is "on" at any one time, thus reducing circuit power consumption and reducing required device sizes. The input switching level is also independent of the supply voltage (18).
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公开(公告)号：EP0163724A4
公开(公告)日：1986-07-17
申请号：EP85900291
申请日：1984-11-16
发明人： YANG TSEN-SHAU
CPC分类号： G05F3/30 , Y10S323/907
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公开(公告)号：EP0064513B1
公开(公告)日：1986-04-23
申请号：EP81902994.3
申请日：1981-10-23
申请人： MOTOROLA, INC.
发明人： WHATLEY, Roger Alan
IPC分类号： G05F3/16
CPC分类号： G05F3/267
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