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391 条记录 (耗时 0.019 秒)

    D/A converter
    42.
    发明公开
    D/A converter 有权
    D / A转换器

    公开(公告)号：EP1189353A2

    公开(公告)日：2002-03-20

    申请号：EP01118913.1

    申请日：2001-08-03

    申请人： Matsushita Electric Industrial Co., Ltd.

    发明人： Matsusaka, Hiromi

    IPC分类号： H03M1/74

    CPC分类号： H03M1/747

    摘要： While a current of a constant current source 503 is equally divided to a plurality of current paths so as to produce a unit current, switches which are series-connected to the respective current paths are controlled by a switch circuit 504 in response to a digital input signal. As a result, since both output currents 505 and 506 whose unit currents are variable can be obtained, a total number of circuit components is reduced, so that not only an occupied area may be reduced, but also resolution in the vicinity of a center may be improved.

    摘要翻译： 当恒定电流源503的电流等分为多个电流路径以产生单位电流时，串联连接到各个电流路径的开关响应于数字输入由开关电路504控制 信号。 结果，由于可以获得单位电流可变的输出电流505和506，所以减少了电路元件的总数，使得不仅占用面积可以减小，而且中心附近的分辨率可以 改进。

    Charge digital-analog converter using insulated gate MOS transistors
    44.
    发明公开
    Charge digital-analog converter using insulated gate MOS transistors 失效
    Digital-Analog-Wandler des Ladungstyps mit Isolierschicht-MOS-Transistoren

    公开(公告)号：EP0833454A1

    公开(公告)日：1998-04-01

    申请号：EP96830491.5

    申请日：1996-09-30

    申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

    发明人： Kramer, Alan ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Rolandi, Pier Luigi ,  Sabatini, Marco

    IPC分类号： H03M1/74

    CPC分类号： H03M1/74

    摘要： The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals, and an output (OUT) for an analog signal, and comprising a charge integration circuit (INT) having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors (M01, M11,M21,M31) corresponding to the plurality of converter inputs, having their source and drain terminals coupled all together and to the input (ND) of the integration circuit (INT), and having control terminals coupleable, under control from the inputs of the plurality, to different references (VCC,GND) of potential having selected fixed values.

    摘要翻译： 本发明涉及具有用于数字信号的多个输入（B0，B1，B2，B3）和用于模拟信号的输出（OUT）的数/模转换器，并且包括电荷积分电路（INT） 具有耦合到转换器输出的输入和输出，以及对应于多个转换器输入的多个浮置栅极MOS晶体管（M01，M11，M21，M31），其源极和漏极端子一起耦合到输入端 （INT）的控制端子（ND），并且具有在多个输入端的控制下可控制的控制端子到具有选定的固定值的电位的不同参考（VCC，GND）。

    Current source driven DA converter and AD using the same
    46.
    发明公开
    Current source driven DA converter and AD using the same 失效
    Stromgesteuerter Digital-Analogumsetzer und Analog-Digitalumsetzer unter Verwendung desselben

    公开(公告)号：EP0708530A1

    公开(公告)日：1996-04-24

    申请号：EP95307418.4

    申请日：1995-10-18

    申请人： AT&T Corp.

    发明人： Gross, George Francis, Jr. ,  Viswanathan, Thayamkulangara Ramaswamy

    IPC分类号： H03M1/74

    CPC分类号： H03M1/765

    摘要： There is disclosed an integrated circuit that includes a digital-to-analog converter (e.g., 10) having a resistor string (e.g., 14) driven by a current source (e.g., 12). The resistor string is coupled to the current source. Intermediate taps (e.g., T₁ through T n+1 ) are defined at the resistor junctions as well the resistor-current source junctions. Switching transistors (e.g., M₁ through M n+1 ) are coupled between an output node and a respective intermediate tap. A selection circuit (e.g., 2) is coupled to a terminal of each switching transistor for selectively switching the transistors to a predetermined state to electrically couple the associated intermediate tap to the output node (e.g., 16).

    摘要翻译： 公开了一种集成电路，其包括具有由电流源（例如12）驱动的电阻串（例如14）的数模转换器（例如，10）。 电阻串耦合到电流源。 中间抽头（例如，T1至Tn + 1）定义在电阻器结以及电阻 - 电流源结。 开关晶体管（例如，M1至Mn + 1）耦合在输出节点和相应的中间抽头之间。 选择电路（例如2）耦合到每个开关晶体管的端子，用于选择性地将晶体管切换到预定状态以将相关联的中间抽头电耦合到输出节点（例如16）。

    Digital-to-analog converter
    48.
    发明公开
    Digital-to-analog converter 失效
    数字 - 模拟转换器

    公开(公告)号：EP0461803A3

    公开(公告)日：1993-12-15

    申请号：EP91305075.3

    申请日：1991-06-05

    申请人： International Business Machines Corporation

    发明人： Chung, Paul Wing-Shing ,  Lowrie, David Scott ,  Saber, Paik ,  Wang, Chorng Kuang

    IPC分类号： H03M1/74 ,  G05F3/26 ,  H03L7/093 ,  G11B20/10 ,  H03M1/66

    CPC分类号： H03M1/0619 ,  G05F3/262 ,  G11B20/10 ,  G11B20/10055 ,  G11B20/1403 ,  H03L7/085 ,  H03M1/747

    摘要： Described is a digital-to-analog converter (46) for use in a timing control loop. The converter includes a plurality of cells (B1....BN), each activated in response to a timing loop control signal. The converter also includes a resistive current mirror, with a first resistance R1, providing a reference current which is mirrored in each cell by a current source FET. Each cell is constructed to switch the current from its current source FET through an output FET when a respective control bit provided to the cell is positive. Otherwise, the current is diverted through a sink FET. All of the cell output FETs are tied to a single resistance R2 which collects the currents of the active cells and provides the AC output of the converter. The converter's output is related only to the ratio R2/R1, thereby decoupling process, temperature, and voltage effects from the output of the converter.

    摘要翻译： 描述了用于定时控制环路中的数字 - 模拟转换器（46）。 该转换器包括多个单元（B1 ... BN），每个单元响应于定时回路控制信号而被激活。 该转换器还包括具有第一电阻R1的电阻电流镜，提供参考电流，该参考电流通过电流源FET镜像在每个单元中。 当提供给单元的相应控制位为正时，每个单元被构造为将来自其电流源FET的电流通过输出FET切换。 否则，电流通过接收器FET转向。 所有单元输出FET都连接到单个电阻R2，该电阻收集有源单元的电流并提供转换器的交流输出。 转换器的输出仅与比率R2 / R1相关，从而使转换器输出的过程，温度和电压影响解耦。

    Digital to analog converter with precise linear output for both positive and negative digital input values
    49.
    发明公开
    Digital to analog converter with precise linear output for both positive and negative digital input values 失效
    数字/模拟转换器，具有一个精确的线性输出，对于正的和负的数字输入变量。

    公开(公告)号：EP0558243A2

    公开(公告)日：1993-09-01

    申请号：EP93301262.7

    申请日：1993-02-22

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Carobolante, Francesco

    IPC分类号： H03M1/66 ,  H03M1/74

    CPC分类号： H03M1/745

    摘要： A circuit and method for converting a digital number to an analog output signal, wherein the most significant bit or "sign" bit of the digital number is used for switching the accumulated currents of the other data bits to a chain of operational amplifiers employing feedback resistors for conversion into an output voltage of magnitude and sign corresponding to the input digital number. A decoding circuit and method enables the circuit to present an output voltage corresponding to the two's-complement of the input digital number.

    摘要翻译： 的电路和方法，用于在模拟输出信号的数字数转换成，worin最显著位或“符号”的数字数的位被用于切换的其他数据位的累积电流的运算放大器采用反馈电阻器的链 用于转换成在幅值的输出电压并签署对应于输入数字号码。 的解码电路和方法能够呈现在输出电压对应于输入数字值的二进制补码的电路。

    Low noise dac current source topology
    50.
    发明公开
    Low noise dac current source topology 失效
    低噪声DAC电流源拓扑

    公开(公告)号：EP0447833A3

    公开(公告)日：1993-07-21

    申请号：EP91102629.2

    申请日：1991-02-22

    申请人： TriQuint Semiconductor, Inc. ,  TEKTRONIX INC.

    发明人： Weiss, Frederick G. ,  Knierim, Daniel G.

    IPC分类号： G05F1/00 ,  H03M1/74 ,  H03M1/06

    CPC分类号： H03M1/0607 ,  G05F1/462 ,  G05F1/468 ,  G05F1/561 ,  H03M1/742

    摘要： An electrical circuit (30) corrects for the presence of noise current and current drift in the currents developed by each current source transistor Q₀, Q₁, Q₂, Q₃, ... Q n in a current source array. The electrical circuit corrects for the presence of noise current and current drift by simultaneously inducing in each current source correction currents whose values sum to cancel the current drift and noise. A noise suppression circuit includes an amplifier (12) having an open loop gain, A v , which is configured to adjust the magnitudes of the multiple currents in response to the introduction of a noise current, i δ , in any one of the currents. The adjustment substantially cancels i δ and thereby substantially reduces the presence of i δ in the output current. The presence of i δ in the output signal is substantially equal to i δ /(1 + A v ).

    摘要翻译： 电路（30）校正由电流源阵列中的每个电流源晶体管Q0，Q1，Q2，Q3，... Qn产生的电流中的噪声电流和电流漂移的存在。 电路通过在每个电流源中同时引起校正电流来纠正噪声电流和电流漂移的存在，校正电流的值相加以消除电流漂移和噪声。 噪声抑制电路包括具有开环增益Av的放大器（12），其被配置为响应于在任何一个电流中引入噪声电流i delta来调整多个电流的幅度。 该调整基本上抵消了i delta，从而显着地减少了输出电流中i delta的存在。 输出信号中Δδ的存在基本上等于i delta /（1 + Av）。