公开(公告)号：EP1131923B1

公开(公告)日：2007-03-21

申请号：EP99931960.1

申请日：1999-06-25

申请人： Level One Communications, Inc.

发明人： CHONG, Simon ,  HUANG, Anguo, Tony ,  BLESZYNSKI, Ryszard ,  STELLIGA, David, A.

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L29/06

CPC分类号： H04Q11/0478 ,  G06F9/54 ,  G06F12/023 ,  H04L12/4608 ,  H04L12/5601 ,  H04L29/12009 ,  H04L29/12018 ,  H04L41/00 ,  H04L45/7453 ,  H04L47/24 ,  H04L49/3009 ,  H04L49/309 ,  H04L49/351 ,  H04L49/602 ,  H04L49/90 ,  H04L49/9026 ,  H04L49/9047 ,  H04L61/10 ,  H04L69/08 ,  H04L69/12 ,  H04L69/32 ,  H04L2012/5617 ,  H04L2012/5679

摘要： Systems and methods for assisting multiple protocol conversion in a network accelerator. A network device includes a transmit processing engine (70), a receive processing engine (60) and one or more memories (80), each memory including one or more buffers for storing packets. When a packet is received, the receive engine (60) adds a 4, 8, 12 or 16-byte tag to the front of the packet on a per-VC basis and stores the packet to a buffer. Additionally, the receive engine (60) is able to add an offset to the starting address of the packet in the buffer relative to the beginning of the buffer. When a packet is to be transmitted, the transmit engine (70) is able to transmit the packet from an address that is offset from the starting address of the buffer by one or more bytes. Additionally, the transmit engine (70) is able to add one of several predefined packet headers on a per-packet basis.

摘要翻译： 在二维链接列表数据结构中排队和排队数据包的系统和方法。 网络处理器处理用于多个虚拟连接（VC）的传输的数据。 处理器为每个VC创建二维链接列表数据结构。 每个数据包的数据字段存储在一个或多个缓冲存储器中。 每个缓冲存储器具有关联的缓冲器描述符，其包括指向缓冲存储器的位置的指针，以及指向与存储相同数据包的数据的缓冲存储器相关联的下一缓冲器描述符的存储器的指针。 每个数据分组还具有相关联的分组描述符，其包括指向与该分组相关联的第一缓冲器描述符的存储器位置的指针，以及指向与排队等待传输的下一个数据分组相关联的分组描述符的存储器位置的指针。 每个VC的VC描述符跟踪下一个分组描述符和要排队的下一个缓冲描述符的存储器位置，以及用于存储下一个分组描述符和下一个要排队的缓冲区描述符的存储单元。

公开(公告)号：EP1494400A2

公开(公告)日：2005-01-05

申请号：EP04077732.8

申请日：1998-05-08

申请人： LEVEL ONE COMMUNICATIONS, INC

发明人： Feuerstraeter, Mark T. ,  Sokol, Michael A. ,  Vogel, David W.

IPC分类号： H04L12/40

CPC分类号： H04L12/40136 ,  H04L12/40 ,  H04L12/4013 ,  H04L12/413 ,  H04L12/46 ,  H04L69/32 ,  H04L2012/445

摘要： A PHY having a media independent interface (MII) providing connections to a MAC or to another PHY is disclosed. The invention provides a mechanism for connecting a first PHY with a second PHY, wherein the PHY may act as the media access control side of the MII. The system includes a selection means for selecting the mode of operation for the PHY, a MII for providing a synchronous digital interface carrying un-encoded data over separate transmit and receive paths and a translation entity for generating output enables for controlling the flow of the data, wherein the translation entity establishes in response to mode being selected a first flow of data for connecting the PHY to a Media Access Control entity or a second flow of data for connecting the PHY to a second PHY. The translation entity muxes data and control signals based upon the mode selection. A translation synchronization entity is provided. The synchronization entity may includes a 10 Mbps synchronization entity and/or a 100 Mbps synchronization entity. The MII receives a transmit and receive clock from a second PHY when the PHY is connected to a second PHY, and the translation synchronization entity synchronizes the internal clocks and the MII transmit and receive clocks. An interface to a 10 or 100 Mbps repeater entity is provided wherein the interface maps a transmit data path from the translation entity to the repeater entity and receive data paths from the repeater entity to the translation entity.

摘要翻译： 具有媒体独立接口（MII）提供到MAC或PHY连接到另一个甲PHY处于游离缺失盘。 本发明提供了用于连接第一PHY与第二PHY，worin所述PHY可以充当MII的媒体访问控制侧的机构。 该系统包括选择装置，用于选择操作模式用于PHY，一个MII用于提供一个同步数字接口通过单独的发射携带未编码数据和接收路径以及用于产生输出的转换实体启用用于控制数据的流动 ，worin翻译实体响应于模式建立被选择的数据的第一流用于PHY连接到媒体访问控制实体或数据的用于PHY连接到第二PHY的第二流动。 在所述模式选择基于所述翻译实体复用器数据和控制信号。 是提供翻译，同步实体。 所述同步实体可以包括一个10 Mbps的同步实体和/或一个100 Mbps的同步实体。 所述MII接收一个发射和当PHY连接到第二PHY从第二PHY接收时钟，和翻译同步实体同步的内部时钟和MII发送和接收时钟。 被提供给一个10或100 Mbps中继器实体的接口worin接口从翻译实体到中继实体映射的发送数据的路径和从中继器实体到翻译实体接收数据路径。

公开(公告)号：EP1013027B1

公开(公告)日：2004-04-21

申请号：EP98945932.6

申请日：1998-09-08

申请人： LEVEL ONE COMMUNICATIONS, INC

发明人： FEUERSTRAETER, Mark, T. ,  HAYDEN, Kirk

IPC分类号： H04L1/12 ,  H04L29/06

CPC分类号： H04L67/32 ,  H04L1/0002 ,  H04L1/0061 ,  H04L12/4013 ,  H04L12/40136 ,  H04L12/413 ,  H04L12/44 ,  H04L29/06 ,  H04L43/00 ,  H04L43/0823 ,  H04L43/16 ,  H04L69/18 ,  H04L69/24 ,  H04L69/323 ,  Y02D50/10

摘要： A network device automatically detects the best protocol a network will support. The network device includes a driver for transmitting data, a receiver for receiving data, and a port operationally coupled to the driver and receiver. The network device further includes negotiation logic coupled to the driver and receiver for selecting a protocol in coordination with other network devices. The network device further includes error detection logic and backs down to a lower transmission rate if errors are detected after the initial negotiation of the selected protocol.

摘要翻译： 网络设备自动检测网络将支持的最佳协议。 网络设备包括用于发送数据的驱动器，用于接收数据的接收器和可操作地耦合到驱动器和接收器的端口。 网络设备还包括耦合到驱动器和接收器的协商逻辑器，用于与其他网络设备协调选择协议。 网络设备还包括错误检测逻辑，并且如果在所选择的协议的初始协商之后检测到错误，则返回到较低的传输速率。

公开(公告)号：EP0972356B1

公开(公告)日：2002-02-13

申请号：EP98913111.5

申请日：1998-03-25

申请人： LEVEL ONE COMMUNICATIONS, INC

发明人： RAO, Sailesh, Krishna

IPC分类号： H04B3/23 ,  H03H17/06

CPC分类号： H04L25/03038 ,  H03H17/06 ,  H03H21/0043 ,  H03H2021/0059 ,  H04B3/235

公开(公告)号：EP1099301A1

公开(公告)日：2001-05-16

申请号：EP99935663.7

申请日：1999-07-15

申请人： LEVEL ONE COMMUNICATIONS, INC

发明人： CHO, Thomas, Byunghak

IPC分类号： H03F3/21 ,  H03F1/56 ,  H03F3/68

CPC分类号： H03F3/68 ,  H03F1/56 ,  H03F3/211 ,  H03F2200/372

摘要： A low noise amplifier circuit provides high gain and an input impedance matching a source output impedance by combining two amplifiers having different operational characteristics in parallel. The amplifier circuit includes a first amplifier having an input impedance matching a source and a gain less than a system requirement and a second amplifier having a gain meeting the system requirement and an input impedance substantially higher than the input impedance for the first amplifier, the second amplifier being connected in parallel to the first amplifier. The first amplifier includes an input and an output and the second amplifier includes an input and an output, the input to the first amplifier and the input to the second amplifier being connected to the source. A summer is provided for combining an output signal from the first amplifier with an output of the second amplifier. The input impedance of the first amplifier and the input impedance of the second amplifier provide an effective circuit impedance equal to an output impedance of the source. The first and the second amplifier include low noise RF amplifiers. Thus, the first and second amplifier provide an effective gain meeting the system requirement and an effective input impedance matching an output impedance of the source.

公开(公告)号：EP1085692A1

公开(公告)日：2001-03-21

申请号：EP99307409.5

申请日：1999-09-20

申请人： LEVEL ONE COMMUNICATIONS, INC

发明人： Sokol, Michael A.

IPC分类号： H04L12/22

CPC分类号： H04L41/28 ,  H04L12/22 ,  H04L63/1441 ,  H04L63/20

摘要： A security device for use in communications network devices, such as multi-port repeaters, in local area networks to prevent eavesdropping by overwriting the data with an invalid symbol in the data communication packets transmitted to all unintended transceivers connected to the communications network device. Confidential or user sensitive information is not conveyed to the unintended transceivers since the invalid symbol is defined independent of the data. The invalid symbol unambiguously informs the unintended transceivers that the data in the data packet is invalid.

摘要翻译： 用于在通信网络设备，比如多端口中继器使用的安全装置，在局域网通过在发送给连接到通信网络设备的所有非预期的收发器的数据通信的数据包的无效符号重写数据，以防止预防窃听。 由于无效符号被定义独立于数据的机密或敏感用户信息不传送到非预期的收发器。 无效码元在数据包中明确时通知非预期收发器阙乐数据是无效的。

公开(公告)号：EP1076962A1

公开(公告)日：2001-02-21

申请号：EP99916565.7

申请日：1999-04-09

申请人： LEVEL ONE COMMUNICATIONS, INC

发明人： HEGDE, Gopal, Dattaray

IPC分类号： H04L12/46

CPC分类号： H04L12/4625

摘要： A packet forwarding method and apparatus performs multiprotocol routing (for IP and IPX protocols) and switching. Incoming data packets are examined and the flow (i.e., source and destination addresses and source and destination socket numbers) with which they are associated is determined. A flow table contains forwarding information that can be applied to the flow. If an entry is not present in the table for the particular flow, the packet is forwarded to the CPU to be processed. The CPU can then update the table with new forwarding information to be applied to all future packets belonging to the same flow. When the forwarding information is already present in the table, packets can thus be forwarded at wire speed. A dedicated ASIC is preferably employed to contain the table, as well as the engine for examining the packets and forwarding them according to the stored information. Decision-making tasks are thus more efficiently partitioned between the switch and the CPU so as to minimize processing overhead.

公开(公告)号：EP1010246A1

公开(公告)日：2000-06-21

申请号：EP98922221.1

申请日：1998-05-12

申请人： LEVEL ONE COMMUNICATIONS, INC

发明人： CAMAGNA, John, R. ,  TAKATORI, Hiroshi ,  AN, Ping

IPC分类号： H03H21/00

CPC分类号： H03H21/0012

摘要： An efficient implementation of a multirate filter with delayed error feedback is disclosed. The multirate filter prevents the instruction processing rate requirement from increasing by performingthe interpolation and decimation in the LMS filter element at the same time. The multirate filter calculates an ith coefficient value, wherein i is a set of consecutive integers, by obtaining an (i-1)th error value, obtaining an (i-1)th error value, multiplying the (i-1)th error value to obtain an ith coefficient product, obtaining Mth coefficient value from a coefficient register, wherein M is a predetermined integer, and adding the Mth coefficient value to the ith coefficient product to obtain an ith coefficient value; and calculates an ith data value by multiplying the (i-1)th data value and the Mth coefficient value to produce ith convolution product and adding a (I-1)th convolution sum to the ith convolution product to produce an ith convolution sum. Obtaining the Mth coefficient value decimates the convolution by M and interpolates the error by M. Otaining the (i-1)th data value further comprises incrementing a data register by one when new data is not written into the data register.

公开(公告)号：EP0980612A1

公开(公告)日：2000-02-23

申请号：EP98921061.2

申请日：1998-05-08

申请人： LEVEL ONE COMMUNICATIONS, INC

发明人： FEUERSTRAETER, Mark, T. ,  SOKOL, Michael, A. ,  VOGEL, David, W.

IPC分类号： H04L12/46 ,  H04L12/413

CPC分类号： H04L12/40136 ,  H04L12/40 ,  H04L12/4013 ,  H04L12/413 ,  H04L12/46 ,  H04L69/32 ,  H04L2012/445

摘要： A PHY having a media independent interface (MII) providing connections to a MAC or to another PHY is disclosed. The invention provides a mechanism for connecting a first PHY with a second PHY, wherein the first PHY may act as the media access control side of the MII. The system includes a selection means for selecting the mode of operation for the PHY, a MII for providing a synchronous digital interface carrying un-encoded data over separate transmit and receive paths and a translation entity for generating output enables for controlling the flow of the data, wherein the translation entity establishes in response to mode being selected a first flow of data for connecting the PHY to a Media Access Control entity or a second flow of data for connecting the PHY to a second PHY. The translation entity muxes data and control signals based upon the mode selection. A translation synchronization entity is provided. The synchronization entity may include a 10 Mbps synchronization entity and/or a 100 Mbps synchronization entity. The MII receives a transmit and receives clock from a second PHY when the PHY is connected to a second PHY, and the translation synchronization entity synchronizes the internal clocks and the MII transmit and receive clocks. An interface to a 10 or 100 Mbps repeater entity is provided wherein the interface maps a transmit data path from the translation entity to the repeater entity and receive data paths from the repeater entity to the translation entity.

公开(公告)号：EP0965198A1

公开(公告)日：1999-12-22

申请号：EP98908905.0

申请日：1998-03-04

申请人： LEVEL ONE COMMUNICATIONS, INC

发明人： TAKATORI, Hiroshi ,  LING, Stanley, K. ,  GATTANI, Amit ,  CAMAGNA, John, R.

IPC分类号： H04L7

CPC分类号： H04L7/0058 ,  H04L7/0062 ,  H04L7/0083

摘要： A timing recovery circuit is disclosed that prevents phase error over-compensation. The timing recovery circuit includes a phase scanner for determining when phase error over-compensation has occurred and generating a signal for preventing dual phase compensation in response thereto, thereby providing an accurate recovered clock signal. The timing recovery circuit also includes a feed-forward equalizer having a plurality of taps providing coefficients for filtering and adapting the input timing recovery circuit to an input signal. The phase scanner compares the tap coefficients to generate signal for preventing phase over-compensation by the feed-forward equalizer. A phase detector is provided for sampling coefficients from the feed-forward equalizer, error signals and output data and generating a phase signal used to generating the recovered clock signal. The signal for preventing phase over-compensation is mixed with the phase signal to generate the recovered clock signal.