公开(公告)号：EP0833453A1

公开(公告)日：1998-04-01

申请号：EP96830490.7

申请日：1996-09-30

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Kramer, Alan, c/o SGS-Thomson Microelec. S.r.l. ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Leong, Philip, c/o SGS-Thomson Microelec. S.r.l. ,  Rolandi, Pier Luigi ,  Sabatini, Marco, c/o SGS-Thomson Microelec. S.r.l.

IPC分类号： H03M1/74

CPC分类号： H03M1/74

摘要： The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals and an output (OUT) for an analog signal, and comprising a current amplification circuit (AMP) having an input (ND) and an output coupled to the converter output; and a plurality of floating gate MOS transistors (M01, M11, M21, M31) corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference (GND) of potential, drain terminals coupled together and to the input (ND) of the amplification circuit (AMP), and control terminals coupleable, under control from the inputs of the plurality, to different references (GND,VCC) of potential having selected fixed values.

摘要翻译： 数模转换器本发明涉及一种数模转换器，具有用于数字信号的多个输入（B0，B1，B2，B3）和用于模拟信号的输出（OUT），并且包括具有电流放大电路（AMP）的电流放大电路 输入（ND）和耦合到转换器输出的输出; 以及与多个转换器输入对应并且其源极端子耦合在一起的多个浮置栅极MOS晶体管（M01，M11，M21，M31）和耦合在一起的电位漏极端子的第一参考（GND） （ND），以及控制端子，可在多个输入端的控制下耦合到具有所选择的固定值的不同参考电压（GND，VCC）。

公开(公告)号：EP0833347A1

公开(公告)日：1998-04-01

申请号：EP96830498.0

申请日：1996-09-30

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Kramer, Alan c/o SGS-Thomson Microelectr. S.r.l. ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Rolandi, Pier Luigi ,  Sabatini, Marco

IPC分类号： G11C27/00

CPC分类号： G11C27/005

摘要： The programmable reference voltage source (1) includes a nonvolatile memory cell (2), the floating-gate region (3) of which stores electric charges determining a memorized threshold value. The drain terminal (4) of the cell is biased at a constant voltage (D r ), and the source terminal (14) is connected to a constant-current source (21) and to the inverting input of an operational amplifier (21) having the noninverting input connected to a reference voltage (V r ) and the output (10) connected to the gate terminal (8) of the cell (2). By defining the threshold of the cell (2) as the gate voltage (measured with respect to ground) capable of causing the cell (2) to be flown by the current (I s ) set by the current source (22), the output voltage (V o ) of the operational amplifier (21) equals the threshold and may be used as a programmable reference in analog memories.

摘要翻译： 可编程参考电压源（1）包括非易失性存储单元（2），其浮动栅极区域（3）存储确定存储的阈值的电荷。 电池的漏极端子（4）以恒定电压（Dr）被偏置，并且源极端子（14）连接到恒流源（21）和与运算放大器（21）的反相输入端相连， 连接到参考电压（Vr）的非反相输入和连接到单元（2）的栅极端子（8）的输出（10）。 通过将电池（2）的阈值定义为能够使电池（2）由电流源（22）设定的电流（Is）流动的栅极电压（相对于地测量），输出电压 运算放大器（21）的电压（Vo）等于阈值，并且可以用作模拟存储器中的可编程参考。

公开(公告)号：EP0833267A1

公开(公告)日：1998-04-01

申请号：EP96830492.3

申请日：1996-09-30

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Kramer, Alan ,  Canegallo, Roberto ,  Rolandi, Pier Luigi ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Sabatini, Marco

IPC分类号： G06G7/60 ,  G06G7/26

CPC分类号： G11C16/0441 ,  G06G7/26 ,  G06N3/0635

摘要： The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors (M1,M2) having source and drain terminals which are coupled together and to an injection node (ND), and at least one corresponding pair of generators (G1,G2) of substantially step-like voltage signals (S1,S2) having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors (M1,M2);
the signal generators (G1,G2) being such that the initial value of a first (S1) of the signals is substantially the equal of the final value of a second (S2) of the signals, and that the final value of the first signal (S1) is substantially the equal of the initial value of the second signal (S2).

摘要翻译： 本发明的电荷注入电路包含至少一对浮置栅的MOS晶体管（M1，M2），其耦接在一起，并且至注射节点（ND），其具有源极和漏极端子，以及至少一个对应的一对发电机（G1 的，基本上阶梯状电压信号的G2）（S1，S2），其具有（初始分别耦合到所述的控制端子值和最终值，并且具有输出晶体管M1，M2）; 信号发生器被检查（G1，G2）做了第一（S1）的信号的初始值大致相等的信号的第二（S2）的最终值，并且做的第一信号的最终值 （S1）基本上等于所述第二信号（S2）的初始值的。

公开(公告)号：EP0859333A1

公开(公告)日：1998-08-19

申请号：EP97830053.1

申请日：1997-02-12

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Kramer, Alan, c/o SGS-Thomson Microelectronics ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Navoni, Loris ,  Rolandi, Pierluigi

IPC分类号： G06K9/00 ,  G06K9/68

CPC分类号： G06K9/723 ,  G06K9/6857 ,  G06K2209/01

摘要： The method of coding characters for word recognition in a word recognition device comprises the steps of: reading a plurality of known words (19); detecting morphological similarities between the characters of the alphabet forming the known words (20-22); associating with each character a weight (23), by associating morphologically similar characters with similar weights; and storing the weights in a data memory of the word recognition device. To detect the morphological similarity between the characters, a confusion table is determined, by plotting data relating to the probability of confusing a character belonging to the known words with other characters; on the basis of the confusion table, a similarity graph is determined in which the characters of the alphabet which can easily be confused with one another are connected by connection lines; and on the basis of the similarity graph, an adjacency list is determined, including the characters of the alphabet arranged by degree of reciprocal similarity. The weights are then fixed in such a way that similar weights correspond to adjacent characters in the adjacency list.

摘要翻译： 在一个字识别装置的编码字识别字符的方法，包括以下步骤：读出的已知字的多个（19）; 检测所述字母表的形成已知单词（20-22）中的字符之间的相似形态学; 与每个字符相关联的权重（23），通过关联具有类似的权重形态相似字符; 和存储在所述字识别装置的数据存储器中的权重。 为了检测人物之间的形态相似，一个混淆表是确定性的开采，通过绘制有关的数据混淆属于与其他人物的已知字的字符的概率; 混淆表的基础上，一个相似曲线图确定的开采在哪家可以容易地与通过连接线被连接彼此混淆字母表中的字符; 和相似图形的基础上，邻接表上上确定性开采，包括相互的相似性程度，排列在字母表的字符。 然后，权重是固定在寻求一种方式也做了类似的权重对应相邻字符的邻接表。

公开(公告)号：EP0859366A1

公开(公告)日：1998-08-19

申请号：EP97830054.9

申请日：1997-02-12

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Navoni, Loris ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Kramer, Alan c/o SGS-Thomson Microelectronics Srl. ,  Rolandi, Pierluigi

IPC分类号： G11C11/00 ,  G06F17/30

CPC分类号： G06F17/30985 ,  G11C15/046 ,  Y10S707/961 ,  Y10S707/99945

摘要： The memory device includes an associative memory (10) for the storage of data belonging to a plurality of classes. The associative memory comprises a plurality of memory locations aligned along rows and columns for the storage of the data along the rows. Each memory row comprises a plurality of groups of memory locations each storing a respective datum, wherein groups of memory locations adjacent along one and the same row store data belonging to different classes, and groups of memory locations adjacent in the direction of the columns and disposed on different rows store data belonging to one and the same class. Each class comprises data having a different maximum length. The device is particularly suitable for the storage of words belonging to a dictionary for the automatic recognition of the words in a written text.

摘要翻译： 存储器件包括用于存储属于多个类别的数据的关联存储器（10）。 关联存储器包括沿着行和列对准的多个存储器位置，用于沿行存储数据。 每个存储器行包括多组存储单元，每组存储相应的数据，其中沿同一行相邻的存储单元组存储属于不同类别的存储器单元组，以及在列的方向上相邻的存储器单元组 在不同的行上存储属于同一个类的数据。 每个类包括具有不同最大长度的数据。 该装置特别适用于存储属于用于自动识别书面文本中的单词的字典的单词。

公开(公告)号：EP0859332A1

公开(公告)日：1998-08-19

申请号：EP97830052.3

申请日：1997-02-12

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Navoni, Loris ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Kramer, Alan, c/o SGS-Thomson Microelectronics ,  Rolandi, Pierluigi

IPC分类号： G06K9/00 ,  G06F17/30

CPC分类号： G06F17/30985 ,  G11C15/046 ,  Y10S707/99936

摘要： The word recognition device (1) uses an associative memory (10) to store a plurality of coded words in such a way that a weight is associated with each character of the alphabet of the stored words, wherein equal weights correspond to equal characters. To perform the recognition, a dictionary of words is first chosen (30); this is stored (31, 32) in the associative memory according to a pre-determined code; a string of characters which correspond to a word to be recognized is received; a sequence of weights corresponding to the string of characters received is supplied (33) to the associative memory; the distance between the word to be recognized and at least some of the stored words is calculated in parallel (34) as the sum of the difference between the weights of each character of the word to be recognized and the weights of each character of the stored words; the minimum distance is identified; and the word stored in the associative memory having the minimum distance is stored (35).

摘要翻译： 字识别装置（1）使用关联存储器（10）来存储多个编码字，使得权重与存储字的字母表的每个字符相关联，其中相等的权重对应于相等的字符。 要进行识别，首先选择一个字典（30）; 根据预定的代码将其存储在联想存储器中（31,32）; 接收与要识别的字对应的一串字符; 将与所接收的字符串对应的权重序列提供给关联存储器（33） 要被识别的单词和至少一些所存储的单词之间的距离被并行计算（34），作为要识别的单词的每个字符的权重与所存储的每个字符的权重之差的和 话; 确定最小距离; 并存储具有最小距离的关联存储器中存储的字（35）。

公开(公告)号：EP0774726A1

公开(公告)日：1997-05-21

申请号：EP95830466.9

申请日：1995-11-03

申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

发明人： Chinosi, Mauro ,  Canegallo, Roberto ,  Kramer, Alan ,  Guerrieri, Roberto

IPC分类号： G06G7/60

CPC分类号： G06N3/0635

摘要： The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits (Ci) operating in parallel and each having at least a first and second input terminals and designed to receive respectively an analog voltage-comparison signal (RAMP) and analog voltage signals (Vi) of predetermined value and at least one output terminal for digital voltage signals (Voi).
This selector device 1 also comprises at least one logic circuit (L) having a plurality of input terminals each connected to a corresponding output terminal of the comparator circuits (Ci) and at least one output terminal.
Finally said selector 1 incorporates at least one plurality of latches (Mi) each having at least one input terminal connected to the output terminal of a corresponding comparator circuit (Ci) and at least one drive terminal coupled to the output terminal of the logic circuit (L) with each of said memory circuits (Mi) having at least one output terminal corresponding to an output of the selector.

摘要翻译： 本发明涉及一种模拟电压信号选择器装置，其类型包括至少一个并联工作的多个比较器电路（Ci），并且每个至少具有第一和第二输入端子，并被设计成分别接收模拟电压比较 信号（RAMP）和模拟电压信号（Vi）以及数字电压信号（Voi）的至少一个输出端子。 该选择器装置1还包括具有多个输入端的至少一个逻辑电路（L），每个输入端连接到比较器电路（Ci）的相应输出端和至少一个输出端。 最后，所述选择器1包括至少一个多个锁存器（Mi），每个锁存器具有连接到对应比较器电路（Ci）的输出端的至少一个输入端和耦合到逻辑电路的输出端的至少一个驱动端（ L），其中每个所述存储器电路（Mi）具有对应于选择器的输出的至少一个输出端子。

公开(公告)号：EP0840452A1

公开(公告)日：1998-05-06

申请号：EP96830551.6

申请日：1996-10-30

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Kramer, Alan, c/o SGS-Thomson Microelectronics Srl ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Leong, Philip, c/o SGS-Thomson ,  Onorato, Marco ,  Rolandi, Pier Luigi ,  Sabatini, Marco, c/o SGS-Thomson

IPC分类号： H03K19/00 ,  H03M1/00 ,  H03M1/36 ,  H03M1/46 ,  H03M1/50

CPC分类号： H03K5/08 ,  H03K19/0027 ,  H03M1/36 ,  H03M1/46

摘要： This invention relates to a voltage comparator with an input (Vin) for an analog signal and an output (Vout) for a digital signal, comprising an inverter (P1,IG) which has an input coupled to the comparator input and an output coupled to the comparator output, and comprising at least two MOS transistors (P1,IG) coupled to each other, at least one (IG) of the two MOS transistors being of the floating gate type.

摘要翻译： 本发明涉及对输入端（Vin）和电压比较器，用于在模拟信号，并用于将数字信号输出（VOUT），逆变器，包括：（P1，IG），其具有耦合到所述比较器输入，并在耦合到输出输入 比较器的输出，以及包括两个MOS晶体管被浮置栅型中的至少两个MOS晶体管耦合到海誓山盟（P1，IG），至少一个（IG）。

公开(公告)号：EP0833454A1

公开(公告)日：1998-04-01

申请号：EP96830491.5

申请日：1996-09-30

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Kramer, Alan ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Rolandi, Pier Luigi ,  Sabatini, Marco

IPC分类号： H03M1/74

CPC分类号： H03M1/74

摘要： The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals, and an output (OUT) for an analog signal, and comprising a charge integration circuit (INT) having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors (M01, M11,M21,M31) corresponding to the plurality of converter inputs, having their source and drain terminals coupled all together and to the input (ND) of the integration circuit (INT), and having control terminals coupleable, under control from the inputs of the plurality, to different references (VCC,GND) of potential having selected fixed values.

摘要翻译： 本发明涉及具有用于数字信号的多个输入（B0，B1，B2，B3）和用于模拟信号的输出（OUT）的数/模转换器，并且包括电荷积分电路（INT） 具有耦合到转换器输出的输入和输出，以及对应于多个转换器输入的多个浮置栅极MOS晶体管（M01，M11，M21，M31），其源极和漏极端子一起耦合到输入端 （INT）的控制端子（ND），并且具有在多个输入端的控制下可控制的控制端子到具有选定的固定值的电位的不同参考（VCC，GND）。

公开(公告)号：EP0833344A1

公开(公告)日：1998-04-01

申请号：EP96830497.2

申请日：1996-09-30

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Kramer, Alan c/0 SGS-Thomson Microelectr. S.r.l. ,  Canegallo, Roberto ,  Chinosi, Mauro ,  Gozzini, Giovanni ,  Rolandi, Pier Luigi ,  Sabatini, Marco

IPC分类号： G11C15/00

CPC分类号： G11C15/00 ,  G11C15/046

摘要： An input structure (1) for associative memories, including an array of elementary cells (2), a number of input lines (20), a number of output lines (30), a number of address lines (40), and a number of enabling lines (50). Each elementary cell (2) is formed by a D type latch (3) having a data input connected to one of the address lines (40) and an enabling input connected to one of the enabling lines (50), and by a switch (4) connected between an input line and an output line, and having a control input connected to the output of a respective latch to selectively connect the respective input line (20) and output line (30) according to the data stored in the latch.

摘要翻译： 一种用于关联存储器的输入结构（1），包括基本单元阵列（2），多个输入线（20），多个输出线（30），多个地址线（40）和数字 的启用线（50）。 每个单元（2）由D型锁存器（3）形成，D型锁存器（3）具有连接到一条地址线（40）的数据输入和连接到一条使能线（50）的使能输入端和一个开关（ 4），其连接在输入线和输出线之间，并且具有连接到相应锁存器的输出的控制输入，以根据存储在锁存器中的数据选择性地连接相应的输入线（20）和输出线（30）。