公开(公告)号：EP1905897A1

公开(公告)日：2008-04-02

申请号：EP06761432.1

申请日：2006-07-14

申请人： Yuan, Qiang

发明人： Yuan, Qiang

IPC分类号： E01B3/46 ,  B29C47/02

CPC分类号： B29C47/021 ,  B29C47/0016 ,  B29K2021/00 ,  B29K2023/06 ,  B29K2023/12 ,  B29K2025/00 ,  B29K2105/0044 ,  E01B3/46

摘要： This invention discloses a wholly wrapped railroad crosstie. It is composed of an inner core and a shell that is made of deformable composite materials. The shell is molten and united together with the inner core as a whole when it is formed. The shell covers the inner core wholly. There's no seam on the crosstie at all. So it successfully avoids the separation and friction of the crosstie. It greatly increases the reliability and service life of the crosstie. And it reduces the cost of maintenance.

摘要翻译： 本发明公开了一种完全包裹的铁路交叉。 由可变形复合材料制成的内芯和外壳组成。 壳体在形成时整体熔化并与内芯结合在一起。 外壳完全覆盖内芯。 根本就没有缝合线。 所以它成功地避免了交叉的分离和摩擦。 大大提高了交叉的可靠性和使用寿命。 并降低维护成本。

公开(公告)号：EP1688845B1

公开(公告)日：2008-03-12

申请号：EP05253300.7

申请日：2005-05-27

申请人： FUJITSU LIMITED

发明人： Shimazaki, Haruo c/o Fujitsu Limited

IPC分类号： G06F13/38

CPC分类号： G06F13/387

公开(公告)号：EP1895470A2

公开(公告)日：2008-03-05

申请号：EP07250116.6

申请日：2007-01-12

申请人： FUJITSU LIMITED

发明人： Yamamoto, Yoshinobu, c/o Fujitsu Limited

IPC分类号： G06T11/60

CPC分类号： G06T1/60

摘要： An image data buffer apparatus includes a memory, and a FIFO control unit configured to cause the memory to operate as a FIFO and having a write pointer indicative of a write position of the memory and a read pointer indicative of a read position of the memory, wherein the FIFO control unit is configured to store image data as a plurality of blocks in the memory at respective positions successively indicated by the write pointer as the image data are supplied as the blocks contained in an image, to read one of the blocks from the memory at a position indicated by the read pointer, to read, from the memory, partial data that is part of at least one block adjacent to the one of the blocks, and to consolidate the one of the blocks and the partial data for transmission as one consolidated block.

摘要翻译： 一种图像数据缓冲装置包括存储器，且经配置以致使作为FIFO来操作存储器中的FIFO控制单元和具有指示指示所述存储器的读出位置的所述存储器的写入位置和读取指针的写入指针， worin FIFO控制单元被配置为存储图像数据作为块在由作为图像数据被提供作为包含在图像中的块，以读取来自所述块中的一个写指针依次指示的respectivement位置存储器中的多个 存储器在由读指针所指示的位置，读，从存储器，部分数据确实是至少一个块邻近的块的一个的一部分，并且巩固块中的所述一个并用于传输作为部分数据 一个合并的块。

公开(公告)号：EP1398815A3

公开(公告)日：2008-02-20

申请号：EP03028185.1

申请日：2000-01-12

申请人： Hitachi Plasma Patent Licensing Co., Ltd.

发明人： Nakahara, Masahiro, Fujitsu Hitachi Plasma Display ,  Tazume, Ryuji, Fujitsu Hitachi Plasma Display Ltd. ,  Miyazaki, Yukinori, Fujitsu Hitachi Plasma Display ,  Nomura, Shinichi, Fujitsu Hitachi Plasma Display ,  Moriyama, Mitsuhir, Fujitsu Hitachi Plasma Display ,  Kanazawa, Yoshikazu, Fujitsu Limited

IPC分类号： H01J17/49

CPC分类号： H01J11/12 ,  H01J11/24 ,  H01J11/28 ,  H01J2211/245

摘要： A plasma display panel of a surface discharge type is disclosed, which can positively generate the discharge for display while suppressing the power consumption even when the number of the electrodes is increased for attaining the high definition. A plurality of display electrode pairs (x,y) are arranged in proximity with each other inside of a pair of substrates opposed to each other with a discharge gap formed therebetween. Each display electrode (x;y) includes a main pattern (3) extending in one direction, independent discharge patterns (2b) each formed for each luminous area corresponding to a display cell, and a plurality of auxiliary patterns (4) for electrically connecting the main pattern (3) and the discharge patterns (2b) to each other. The auxiliary patterns (4) are higher in conductivity than the discharge patterns (2b) in one embodiment, and are integral with the discharge patterns (2b) in another embodiment.

公开(公告)号：EP1845677A2

公开(公告)日：2007-10-17

申请号：EP06253471.4

申请日：2006-06-30

申请人： Fujitsu Ltd.

发明人： Honda, Atsushi, c/o Fujitsu Limited ,  Nakaya, Yuuta, c/o Fujitsu Limited ,  Nakamura, Michiharu, c/o Fujitsu Limited

IPC分类号： H04L27/26

CPC分类号： H04L27/265 ,  H04L27/2633

摘要： The present invention provides a wireless terminal apparatus (10), including a reception unit (11, 12) for receiving a multi-carrier signal generated by applying an N-point (where N is a natural number) inverse fast Fourier transform (IFFT) to a plurality of sub-carriers to which transmission information for a plurality of wireless terminal apparatuses is allocated; a fast Fourier transform unit (15) for extracting a plurality of the sub-carriers from the multi-carrier signal; a thin-out unit (14), being placed at the front stage of the fast Fourier transform unit, capable of changing, from the N points, a sampling number of the multi-carrier signals which are digitalized; and a judgment unit (17) for discerning, based on sub-carrier allocation information accompanying the multi-carrier signal, whether or not the sub-carrier of another wireless terminal apparatus overlaps with that of the wireless terminal apparatus itself in the case of changing the sampling number from the N points, and determining a sampling number for the thin-out unit.

公开(公告)号：EP1841159A2

公开(公告)日：2007-10-03

申请号：EP06253454.0

申请日：2006-06-30

申请人： Fujitsu Ltd.

发明人： Saitou, Naoyuki, Fujitsu Limited

IPC分类号： H04L27/26

CPC分类号： H04L5/023 ,  H04L1/22 ,  H04L27/2626 ,  H04L27/2647 ,  H04W88/08 ,  H04W92/12 ,  Y02D70/00

摘要： The radio communication apparatus includes: one or more radio units (2-i) each with one or more antennas (24-k; k=1 through M) ; a plurality of baseband processing units (11-j; j = 1 through N) which perform baseband signal processing of signals, transceived by said radio units (2-i), in a frequency domain; and a connection interface (12) which interfaces between said radio unit (2-k) and any of said plurality of baseband processing units (11-j) with signals in a frequency domain. With this arrangement, the transmission capacity of an interface inside the radio communication apparatus and power consumption are reduced, and the radio communication apparatus has superior flexibility and functional expandability for various types of services.

摘要翻译： 无线电通信装置包括：一个或多个无线电单元（2-i），每个无线电单元具有一个或多个天线（24-k; k = 1至M）; 多个基带处理单元（11-j; j = 1〜N），其在频域中进行由所述无线单元（2-i）收发的信号的基带信号处理; 以及在所述无线单元（2-k）和所述多个基带处理单元（11-j）中的任何一个之间与频域中的信号进行接口的连接接口（12）。 通过这种布置，减少了无线电通信装置内的接口的传输容量和功率消耗，并且无线电通信装置对于各种类型的服务具有优异的灵活性和功能可扩展性。

公开(公告)号：EP1622167A3

公开(公告)日：2007-09-26

申请号：EP04257448.3

申请日：2004-11-30

申请人： FUJITSU LIMITED

发明人： Tonosaki, Mie, c/o Fujitsu Limited ,  Sakurai, Hitoshi, c/o Fujitsu Limited

IPC分类号： G11C29/00

CPC分类号： G11C29/88 ,  G11C29/789 ,  G11C29/804

摘要： A cache memory (50) built in a processor (10) comprising a plurality of independent memory blocks (53b), pass/fail information memory unit (56a) memorizing a presence/absence of a failure occurring in each of the memory blocks (53b), and a screening control function (54) substituting a sound memory block for a failedmemory block based on a memory content in the pass/fail information memory unit (56a).

公开(公告)号：EP1835404A2

公开(公告)日：2007-09-19

申请号：EP06253125.6

申请日：2006-06-16

申请人： FUJITSU LIMITED

发明人： Machida, Mamoru

IPC分类号： G06F11/16

CPC分类号： G06F11/1625 ,  G06F11/1641 ,  G06F11/2273 ,  H04L1/22 ,  H04L1/24

摘要： An electronic apparatus which is capable of detecting faults that cannot be detected with a fixed signal pattern and which also permits fault detection to be performed even during the operation thereof. Signal processor circuits perform identical signal processing, and a signal router causes the signal being input to an operating signal processor circuit which is performing the signal processing among the signal processor circuits, to be input to an idle signal processor circuit which is not performing the signal processing. A fault detector compares an operating output signal output from the operating signal processor circuit with an idle output signal output from the idle signal processor circuit to detect a fault.

摘要翻译： 一种电子装置，其能够检测不能用固定信号图案检测的故障，并且即使在其操作期间也允许执行故障检测。 信号处理器电路执行相同的信号处理，并且信号路由器将信号输入到在信号处理器电路之间进行信号处理的操作信号处理器电路，输入到不执行信号的空闲信号处理器电路 处理。 故障检测器将来自操作信号处理器电路的操作输出信号与从空闲信号处理器电路输出的空闲输出信号进行比较，以检测故障。

公开(公告)号：EP1820159A1

公开(公告)日：2007-08-22

申请号：EP05848437.9

申请日：2005-11-11

申请人： MOK3, Inc.

发明人： OH, Byong Mok

IPC分类号： G06T15/20 ,  G06T15/70

CPC分类号： G06T13/80 ,  G06T3/0012 ,  G06T3/20 ,  G06T3/60 ,  G06T15/20 ,  G06T15/205 ,  G06T19/003 ,  G06T2210/44 ,  G06T2215/12

摘要： A method and system for creating a transition between a first scene and a second scene on a computer system display, simulating motion. The method includes determining a transformation that maps the first scene into the second scene. Motion between the scenes is simulated by displaying transitional images that include a transitional scene based on a transitional object in the first scene and in the second scene. The rendering of the transitional object evolves according to specified transitional parameters as the transitional images are displayed. A viewer receives a sense of the connectedness of the scenes from the transitional images. Virtual tours of broad areas, such as cityscapes, can be created using inter-scene transitions among a complex network of pairs of scenes.

公开(公告)号：EP1808861A1

公开(公告)日：2007-07-18

申请号：EP07103542.2

申请日：2001-10-02

申请人： Fujitsu Ltd.

发明人： Matsuzaki, Yasurou ,  Suzuki, Takaaki ,  Yamazaki, Masafumi ,  Kawasaki, Kenichi ,  Kamata, Shinnosuke

IPC分类号： G11C8/16

CPC分类号： G11C7/1051 ,  G11C7/1039 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/409 ,  G11C2207/107

摘要： A semiconductor memory device includes a plurality of memory cores and a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

摘要翻译： 半导体存储器件包括多个存储器核和多个N个外部端口，每个N个外部端口接收命令，以及内部电路，其在输入到外部的一个的命令的最小间隔期间执行至少N次访问操作 端口。