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公开(公告)号：EP0096162A1
公开(公告)日：1983-12-21
申请号：EP83102171.2
申请日：1983-03-05
发明人： Nishikawa, Meisei , Kojima, Tadashi
IPC分类号： G11B19/24
CPC分类号： G11B19/24
摘要： The invention relates to a motor control circuit of a data reproduction apparatus, which drives a disk motor (111) to reproduce a data signal recorded together with a sync signal on a recording medium (113) so as to control the disk motor (111) in accordance with a reproduced sync signal. The frequency and phase components of the reproduced sync signal are detected, and first and second motor control signals are produced in accordance with frequency and phase detection signals, respectively. A control circuit (151) detects whether or not the frequency detection signal falls within a predetermined range. If it is determined that the frequency detection signal does not fall within the predetermined range, the second motor control signal is kept at a predetermined value.
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公开(公告)号：EP0056140A2
公开(公告)日：1982-07-21
申请号：EP81110607.9
申请日：1981-12-18
发明人： Kojima, Tadashi , Todokoro, Shigeru
IPC分类号： G11B5/86
CPC分类号： G11B15/125 , G11B5/86 , G11B27/032 , G11B27/36
摘要： A signal copy device for a digital record/reproduction system includes an encoding circuit (12) for producing a first digital encoded signal corresponding to an analog audio signal. The encoding circuit (12) is connected to a first VTR (24) through a switch section (16) of a switch circuit (18) and : a first digital signal processor (22). A second VTR (64) reproduces and generates a digital encoded audio signal to be copied. The switch circuit (18) is connected to the encoding circuit (12) and the second VTR (64). The switch circuit (18) includes two switch sections (16, 28) which operate in cooperation with each other. When a reproduction signal is generated from the second VTR (64), the two switch sections (16, 28) are switched. The reproduction signal is supplied to the first VTR (24) through these switch sections (16, 28), thus accomplishing copying.
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公开(公告)号：EP0056128A2
公开(公告)日：1982-07-21
申请号：EP81110507.1
申请日：1981-12-16
发明人： Nagumo, Masahide , Kojima, Tadashi
CPC分类号： H03L7/1974 , H03L7/08 , H03L7/087
摘要： A phase synchronizing circuit has a phase locked loop including a first phase comparison circuit (13) to which a predetermined input signal is supplied, a voltage controlled oscillator (VCO) (15) for producing an oscillation output the frequency of which is controlled by the output of the first phase comparison circuit, and first frequency dividing means (16, 17, 18) having at least a first frequency divider (16) to divide the output of VCO. The phase synchronizing circuit further includes second frequency dividing means (19, 20) for dividing the output frequency of VCO, a second phase comparison circuit (21) for comparing the phase of a first clock signal (f a ') which is led from first dividing means, with that of a second clock signal (f a ) which is led from second dividing means, and a controlling means for controlling the first frequency divider and second phase comparison circuit so as to synchronize phases of first and second clock signals. The controlling means controls the frequency dividing ratio of first frequency dividing circuit according to the phase difference between first and second clock signals in such a way that the frequency dividing ratio becomes 1/N, 1/(N+1) and 1/{[N+(N+1)]/2} wherein N is a positive integer. Phases of first and second clock signals can be synchronized accurately.
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公开(公告)号：EP0029226A1
公开(公告)日：1981-05-27
申请号：EP80107015.2
申请日：1980-11-13
IPC分类号： G11B5/09
CPC分类号： G11B20/1809
摘要： A processing system for reproduced audio digital signals used in an audio PCM (pulse code modulation) recording/reproducing system using a recording/reproducing apparatus such as a video tape recorder having a dropout-compensation circuit is disclosed. The reproduced signal processing system is connected to receive digital information signals reproduced through the dropout compensation circuit from a recording medium on which audio information signals are recorded in the form of digital data words and includes circuit means (18, 19, 20, 21; 57, 60, 63, 64) for detecting whether a reproduced digital signal has been dropout-compensated or not and circuit means (17; 58, 59) for adding an error pointer to a reproduced digital signal which is detected as being dropout-compensated.
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55.发明公开Enciphering method, deciphering method, recording and reproducing method, deciphering device, deciphering unit device, recording medium, recording-medium manufacturing method, and key control method 失效加密方法，解密方法，记录和重放方法，解密装置，用于解密单元，记录介质，记录介质的制造方法以及密钥的控制方法
公开(公告)号：EP0817185A3
公开(公告)日：1999-11-10
申请号：EP97304636.0
申请日：1997-06-27
CPC分类号： G11B23/284 , G11B20/00086 , G11B20/0021 , G11B20/00253 , G11B20/00557 , G11B23/28 , H04N5/913 , H04N2005/91364
摘要： On a recording medium, first information obtained by enciphering data with the first key and second information obtained by enciphering the first key with each of the predetermined second keys are recorded. A deciphering method is characterized by comprising the steps of inputting the first and second information (S34, S32), deciphering the first key using at least one of the second keys (S33), determining by a specific method that the obtained first key is correct (S33), and then deciphering the data using the first key to obtain the data (S35).
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56.发明公开Information reproducing apparatus, authenticating apparatus, and information processing system 失效Informationswiedergabegerät，Informationsverarbeitungssystem und -verfahren，und Authentifizierungsverfahren
公开(公告)号：EP0893796A2
公开(公告)日：1999-01-27
申请号：EP98113500.7
申请日：1998-07-20
IPC分类号： G11B20/00
CPC分类号： H04N21/4331 , G11B20/00086 , G11B20/0021 , H04N5/85 , H04N9/8042 , H04N9/8063 , H04N9/8205 , H04N9/8227
摘要： In this invention, an information recording/reproducing apparatus (1) has an authentication function and directly transfers information to an MPEG board (134), sub-picture run-length board (135), speech coding/decoding board (136) without using a main CPU (111). Thus, information transfer between the information recording/reproducing apparatus (1) and various processing boards (134, 135, 136) can be performed without using a main controller (111), the load of the main CPU (111) can be alleviated and the main CPU (111) can perform another process during the information transfer period.
摘要翻译： 在本发明中，信息记录/再现装置（1）具有认证功能，并且直接将信息传送到MPEG板（134），副图像游程板（135），语音编码/解码板（136）而不使用 主CPU（111）。 因此，可以在不使用主控制器（111）的情况下执行信息记录/再现装置（1）和各种处理板（134,135,136）之间的信息传送，可以减轻主CPU（111）的负载， 主CPU（111）可以在信息传送期间执行另一处理。
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公开(公告)号：EP0096163B1
公开(公告)日：1988-06-01
申请号：EP83102173.8
申请日：1983-03-05
发明人： Inagawa, Jun , Nagumo, Masahide , Kojima, Tadashi
CPC分类号： H03M13/15 , G06F7/726 , G11B20/1809
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公开(公告)号：EP0096106B1
公开(公告)日：1986-03-19
申请号：EP82109205.3
申请日：1982-10-05
CPC分类号： G11B20/1403 , G11B20/10527
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公开(公告)号：EP0096109A3
公开(公告)日：1984-10-24
申请号：EP82109564
申请日：1982-10-15
发明人： Nagumo, Masahide , Inagawa, June , Kojima, Tadashi
CPC分类号： H03M13/151 , G06F7/724 , G06F7/726 , G11B20/1809
摘要： An error correcting system uses an error location polynominal defined by double correction BCH codes each consisting of the elements of Galois field GF(2m), thereby to generate error locations σ 1 and σ 2 and error patterns e, and e 2 . The system has a first data processing system (401) for performing only additions and multiplications to generate error locations σ 1 and σ 2 and a second data processing system (402) for performing only additions and mutiplica- tions to generate error patterns e 1 and e 2 . The first data processing system (401) comprises a syndrome generator (41), a memory (43), an arithmetic logic unit (44), registers (45A) to (45C), latch circuits (46A) to (46F), registers (47A) to (47F), adder circuits (48A) and (48B) and a zero detector (49). The second data processing system (402) comprises a gate circuit (50), latch circuits (46H) and (46G), an arithmetic logic unit (44), registers (45A) to (45C) and a memory (43).
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公开(公告)号：EP0096165A3
公开(公告)日：1984-10-17
申请号：EP83102308
申请日：1983-03-09
发明人： Inagawa, Jun , Nagumo, Masahide , Kojima, Tadashi
CPC分类号： G06F7/726 , G06F1/0307 , G11B20/1809 , H03M13/15
摘要： Data representing one element α i of a Galois field GF(2 m ) are stored in a first linear shift register (52), and data representing another element α j of the Galois field GF(2 m ) are stored in a second linear shift register (53). 2 m elements of Galois field GF(2 m ) are divided into n groups. A table of the reciprocals of n elements located at specific positions respectively in n groups is stored in a converter (51) which includes a decoder (511) and an encoder (512). The data representing element α j are supplied from the second linear shift register (53) to the decoder (511). If the data representing the reciprocal of element α j are stored in the converter (51), they are read from the encoder (512). If they are not stored in the converter (51), the first linear shift register (52) and the second linear shift register (63) are shifted N times by control pulses generated by a NOR gate (NOR,) and an AND gate (AND, o ) until any one of the reciprocal data are read from the encoder (512), whereby the register (52) supplies data representing α i+N and the register (53) supplies data representing α -(j+N) . A multiplier (54) multiplies element α i by reciprocal α j or multiplies element α 1+N by reciprocal α -(j+N) , thereby performing the division: a i ÷ α j (= α i-j ).
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