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公开(公告)号：EP0488678A2
公开(公告)日：1992-06-03
申请号：EP91310932.8
申请日：1991-11-27
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/17704
摘要： A programmable integrated circuit of the present invention can change the input of serial/parallel input-parallel output means for program data from serial to parallel or vice versa in response to a control signal from control signal input means. Therefore, a program can be written at a relatively low speed through the parallel output of serial input, and a program can be written at a relatively high speed by inputting data in parallel and outputting the input data in parallel. Moreover, the bit width of the aforementioned serial/parallel input-parallel output means can be changed in response to a control signal from control signal input means, whereby bit width for data input, shift and the like can be optimized according to the quantity of programs to be written with the result of improved freedom of users and the reduced time required for writing a large quantity of programs.
摘要翻译： 本发明的可编程集成电路可以响应于来自控制信号输入装置的控制信号，将串行/并行输入并行输出装置的输入改变为串行到并行或反之亦然。 因此，可以通过串行输入的并行输出以相对较低的速度写入程序，并且通过并行输入数据并且并行地输出输入数据，可以以相对高的速度写入程序。 此外，上述串行/并行输入并行输出装置的位宽度可以响应于来自控制信号输入装置的控制信号而改变，从而可以根据数据输入，移位等的位宽来优化数据输入，移位等的位宽度 由于改善了用户的自由度，编写了大量程序所需的时间缩短了这些程序。
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公开(公告)号：EP0450811A3
公开(公告)日：1992-04-08
申请号：EP91302456.8
申请日：1991-03-21
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/1776 , H03K19/1735 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A configurable logic array, includes a plurality of configurable logic cells which include a tristate output buffer (806,906,1006,1106), having an input receiving a logic signal (TY1) from within the configurable logic cell, an output (Y1) connected to the configurable interconnect structure and an output enable input (OE1). A plurality of selectors (1201-1204), controlled by the configuration memory, supply output enable signals for controlling corresponding tristate output buffers (806,906,1006,1106). The inputs to the plurality of selectors include a "common output enable signal," and at least a second logic signal, such as a constant high or constant low logic level. A circuit responsive to program data in the configuration memory and input signals from the interconnect structure generates the common output enable signal. One input of the selector is provided by an invertor (1210,1211,1212,1213) connected from the input of the tristate output buffer to the selector for connecting an output signal to a long line in a wired-AND configuration.
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公开(公告)号：EP0450811A2
公开(公告)日：1991-10-09
申请号：EP91302456.8
申请日：1991-03-21
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/1776 , H03K19/1735 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： A configurable logic array, includes a plurality of configurable logic cells which include a tristate output buffer (806,906,1006,1106), having an input receiving a logic signal (TY1) from within the configurable logic cell, an output (Y1) connected to the configurable interconnect structure and an output enable input (OE1). A plurality of selectors (1201-1204), controlled by the configuration memory, supply output enable signals for controlling corresponding tristate output buffers (806,906,1006,1106). The inputs to the plurality of selectors include a "common output enable signal," and at least a second logic signal, such as a constant high or constant low logic level. A circuit responsive to program data in the configuration memory and input signals from the interconnect structure generates the common output enable signal. One input of the selector is provided by an invertor (1210,1211,1212,1213) connected from the input of the tristate output buffer to the selector for connecting an output signal to a long line in a wired-AND configuration.
摘要翻译： 可配置逻辑阵列包括多个可配置逻辑单元，其包括三态输出缓冲器（806,906,1006,1106），其具有从可配置逻辑单元内接收逻辑信号（TY1）的输入端，连接到 可配置互连结构和输出使能输入（OE1）。 由配置存储器控制的多个选择器（1201-1204）提供用于控制相应三态输出缓冲器（806,906,1006,1106）的输出使能信号。 多个选择器的输入包括“公共输出使能信号”和至少第二逻辑信号，例如恒定的高或恒定的低逻辑电平。 响应于配置存储器中的程序数据和来自互连结构的输入信号的电路产生公共输出使能信号。 选择器的一个输入由从三态输出缓冲器的输入端连接到选择器的逆变器（1210,1211,1212,1213）提供，该选择器用于将输出信号连接到具有线对准配置的长线。
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54.发明公开Register file with programmable control, decode and/or data manipulation 失效注册会计师程序Steuerung，Dekodierung und / oder Datenverarbeitung。
公开(公告)号：EP0450616A2
公开(公告)日：1991-10-09
申请号：EP91105328.8
申请日：1991-04-04
IPC分类号： H03K19/177 , G06F9/22
CPC分类号： H03K19/177 , G06F9/223 , H03K19/17704
摘要： A programmable logic device is constructed having a novel architecture. A plurality of control input signals are applied to a programmable mapping array in order to generate control functions for data path gating, latching, or modification. The programmable control functions provide flexibility to the designer, while the fixed data path logic is independent of the programmable array. The logic array and data path logic are fabricated on the same integrated circuit, therefore obviating the need for input/output buffers which would be necessary if the device were constructed utilizing discrete components. This enhances the performance of the device. Since the data path does not travel through the array, its performance is not affected by the programmability. If desired, the programmable array can be formed of mask programmable devices, fused programmable devices, or register based circuitry, for example, using RAM cells.
摘要翻译： 构造具有新颖结构的可编程逻辑器件。 多个控制输入信号被施加到可编程映射阵列，以便产生用于数据路径选通，锁存或修改的控制功能。 可编程控制功能为设计者提供了灵活性，而固定数据路径逻辑与可编程阵列无关。 逻辑阵列和数据通道逻辑是在相同的集成电路上制造的，因此避免了对使用分立元件构造器件所必需的输入/输出缓冲器的需求。 这增强了设备的性能。 由于数据路径不通过阵列，其性能不受可编程性的影响。 如果需要，可编程阵列可以由掩模可编程器件，融合可编程器件或基于寄存器的电路形成，例如使用RAM单元。
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公开(公告)号：EP0368859B1
公开(公告)日：1991-07-24
申请号：EP88903770.1
申请日：1988-05-05
IPC分类号： G11C17/00
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17712 , H03K19/1778
摘要： By using a programmable circuit arrangement it is possible to effect the logical connection of binary input signals. The arrangement comprises a matrix (MA) of transmission lines (DL) and coupling lines (KL) at whose coupling points are arranged coupling elements (KE) according to a function table to be produced. The coupling elements (KE) can assume three different states, the first corresponding to a binary 1, the second to a binary 0 and the third to a binary 1 or a binary 0. Each data transmission line (DL) can be operated as an input or an output by means of a control signal (ST) applied to an input circuit and to an output circuit (AG). The input signals coupled to a coupling line (KL) by data transmission lines operated in the input mode are subjected, on the coupling line, to an AND-connection. On the other hand, the signals coupled by the coupling lines (DL) to a data transmission line (DL) operated in the output mode are subjected, on the data coupling line, to an OR-connection. Depending on the state of the coupling elements (KE), set in accordance with a function table, it is possible to achieve different connections by using the data transmission lines (DL) as inputs and as outputs.
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56.发明公开Programmable gate array with improved interconnect structure, input/output structure and configurable logic block 失效可编程门阵列与改进的连接结构中，输入/输出结构和可配置逻辑块。
公开(公告)号：EP0415542A2
公开(公告)日：1991-03-06
申请号：EP90307974.7
申请日：1990-07-20
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17744
摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.
摘要翻译： 以对称的互连结构的可编程门阵列具有改进的互连结构在功能有助于多源网络中，很长的距离在整个阵列信号的通信，和建立网络。 互连包括用于阵列中的每个可配置逻辑模块八个邻居，包括相邻配置逻辑块和下一个相邻的可配置逻辑块的直接连接。 因此，互连件包括由可配置逻辑块的输出来驱动，但通过互连到任何特定的逻辑块的输入端不确认未提交的延绳。 相反，未提交的延绳致力于到互连的其它节段的连接。 该互连结构包括在所述互连件的水平和垂直总线的交点，从而交错的开关矩阵。 改建动力装置的缓冲器确实是在两个方向上配置与在互连双向线路相关联，并且包括一个旁通通道。该互连提供有关从关闭芯片控制信号的通信，从所述阵列中的任何可配置的逻辑块，并从输入/ 输出结构的阵列，以任何或所有其它可配置逻辑块和输入/输出块阵列中英寸
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57.发明公开Programmable logic device with array blocks connected via a programmable interconnect array 失效具有阵列的可编程逻辑器件通过可编程互连连接
公开(公告)号：EP0340890A3
公开(公告)日：1991-01-16
申请号：EP89301780.6
申请日：1989-02-23
申请人： ALTERA CORPORATION
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H01L2224/05554 , H01L2224/49113 , H03K19/17704 , H03K19/17728
摘要： A programmable logic device having a relatively small number of programmable product terms (OE,SETN,P0,P1,P2,INV,ACLK,CLEARN) ("P-terms") feeding each fixed combinatorial logic device (51), and additional "expander" programmable P-terms (EXP1,EXP2) which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array (60) is provided to allow certain inputs (40) to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.
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58.发明公开
公开(公告)号：EP0277152A4
公开(公告)日：1991-01-02
申请号：EP87904763
申请日：1987-06-26
发明人： TURNER, JOHN, E.
IPC分类号： G06F12/14 , G06F21/02 , G06F21/24 , G11C7/24 , G11C16/22 , G11C17/18 , H03K19/177 , G06F7/38
CPC分类号： H03K19/17704 , G11C7/24 , G11C16/22 , G11C17/18 , H03K19/17708 , H03K19/17768
摘要： A data security fuse system (35) for allowing one-time programmability of protected data cells in a reprogrammable logic device (10), which may determine, for example, the logic architecture of the device. The system includes a fuse enable circuit (100) which may be erased to the disabled state only prior to packaging of the device during manufacture. The protected data cells may be selected for programming by a decoder (30) which decodes cell selection signals. A security fuse circuit (300) is enabled by a fuse enable signal (SFE) from the activated fuse enable circuit. The security fuse circuit (300) allows the protected cells to be selected once for programming after the system has been activated, and thereafter defeats any attempts to access the protected data cells.
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公开(公告)号：EP0394575A1
公开(公告)日：1990-10-31
申请号：EP89304285.3
申请日：1989-04-28
申请人： Xilinx, Inc.
发明人： Kaplinsky, Cecil H.
IPC分类号： H03K19/177
CPC分类号： H03K19/17764 , H03K19/17704 , H03K19/17736 , H03K19/17792 , H04Q3/521
摘要： A programmable logic device architecture having a matrix of smaller functional units (20-28), each of which being a programmable logic array, and a set of fixed conductive lines (31, 32) connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices (33). The input pins (34) can be programmably connected to any input of any functional unit (20-28), and the outputs of functional units can be programmably connected to any input of any functional unit (20-28) or any output pin (40). The interconnection matrices (33, 38, 44) may be a simple array of crossing conductive lines with crossings connected by fuses, EPROM, or EEPROM switches or may have additional series switches to limit the effective impedance so as to speed propagation through these matrices. A fast path through one functional unit bypassing the interconnection matrices is available for a limited number of input and output pins. Multiplexers and other structures may be provided at ends of the fixed conductive lines to enable exhaustive testing of individual functional units, interconnections and logic, and structure may also be provided for on-chip monitoring of state information and providing the information to the external world when certain preselected events happen.
摘要翻译： 一种具有较小功能单元（20-28）的矩阵的可编程逻辑器件架构，每个功能单元（20-28）是可编程逻辑阵列，以及一组连接到功能单元输入和输出的固定导线（31,32），导电 形成可编程互连矩阵（33）的线。 输入引脚（34）可以可编程地连接到任何功能单元（20-28）的任何输入，并且功能单元的输出可以可编程地连接到任何功能单元（20-28）或任何输出引脚 40）。 互连矩阵（33,38,44）可以是交叉导线的简单阵列，其中交叉通过熔丝，EPROM或EEPROM开关连接，或者可以具有附加的串联开关以限制有效阻抗，以便加速通过这些矩阵的传播。 绕过互连矩阵的一个功能单元的快速通路可用于有限数量的输入和输出引脚。 可以在固定导线的端部设置多路复用器和其他结构，以便能够对各个功能单元，互连和逻辑进行详尽的测试，并且还可以提供用于片上监视状态信息并且将信息提供给外部世界的结构 某些预选事件发生。
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公开(公告)号：EP0247502B1
公开(公告)日：1990-10-24
申请号：EP87107285.6
申请日：1987-05-19
IPC分类号： H03K19/177
CPC分类号： G06F7/5057 , G01R31/318516 , H03K19/177 , H03K19/17704
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