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100 条记录 (耗时 0.013 秒)

    Automatic test equipment with internal high speed interconnections
    52.
    发明授权
    Automatic test equipment with internal high speed interconnections 有权
    自动测试设备内部的高速连接

    公开(公告)号：EP1071962B1

    公开(公告)日：2003-12-17

    申请号：EP99918533.3

    申请日：1999-04-13

    申请人： TERADYNE, INC.

    发明人： CZAMARA, Allen

    IPC分类号： G01R31/319 ,  G01R31/3167

    CPC分类号： G01R31/31921 ,  G01R31/3167 ,  G01R31/31907 ,  G01R31/3191

    摘要： A tester is disclosed in which state coherency is maintained between functional blocks of the tester by way of a novel state distribution and recombination network. The network includes a plurality of nodes configured to provide point-to-point links can be adjusted by selecting a suitable node configuration and by programming delay circuitry included in each node. The network therefore maintains state coherence between the functional blocks by ensuring that delays throughout the test system are both deterministic and adjustable. The tester is particularly useful for testing complex, mixed-signal semiconductor devices.

    ANALOG CLOCK MODULE
    53.
    发明授权
    ANALOG CLOCK MODULE 有权
    模拟时钟模块

    公开(公告)号：EP1151312B1

    公开(公告)日：2003-01-02

    申请号：EP99953024.9

    申请日：1999-10-01

    申请人： TERADYNE, INC.

    发明人： GAGE, Robert, B.

    IPC分类号： G01R31/3167 ,  G01R31/30

    CPC分类号： G01R31/3167 ,  G01R31/2841 ,  G01R31/30 ,  G01R31/3191 ,  G01R31/31922 ,  H03L7/18 ,  H03L7/1806

    摘要： An analog clock apparatus is disclosed including a digital clock source for producing a digital waveform of a predetermined frequency and a direct-digital-synthesizer. The synthesizer has an input to receive the digital waveform and is operative to generate a resultant analog waveform. Prediction logic is coupled to the digital clock source and the synthesizer for determining the relative phase relationships between the digital waveform and the analog waveform. The prediction logic is responsive to a prediction clock having a clock frequency approximating that of said digital clock source.

    Method and apparatus for analysing a source current waveform in a semiconductor integrated circuit
    54.
    发明公开
    Method and apparatus for analysing a source current waveform in a semiconductor integrated circuit 有权
    一种用于在半导体集成电路分析的源极电流的波形的方法和装置

    公开(公告)号：EP1229462A1

    公开(公告)日：2002-08-07

    申请号：EP01126335.7

    申请日：2001-11-06

    申请人： Semiconductor Technology Academic Research Center

    发明人： Nagata, Makoto ,  Iwata, Atsushi

    IPC分类号： G06F17/50 ,  G01R31/30 ,  G01R31/3167

    CPC分类号： G06F17/5036 ,  G01R31/3004

    摘要： The invention provides a method of analyzing a source current at a higher speed and an enhanced accuracy in a semiconductor integrated circuit including a digital circuit. The method to analyze a waveform of the source current, with consideration of re-distribution of charges throughout the digital circuit in the semiconductor integrated circuit, expressing the digital circuit with series of parasitic capacitors ΣC ch,↑ (nT) and ΣC ch,↓ (nT) to be charged and connected between the source and the ground lines. The capacitor series are calculated in time series based on the distribution of switching operations of the logic gates included in the digital circuit. An analysis model for determining the waveform of the source current in the digital circuit is obtained by connecting the parasitic capacitor series with a couple of respective parasitic impedances Z d and Z g of the source line and the ground line.

    摘要翻译： 本发明提供了以较高的速度和在半导体集成电路包括数字电路精度提高分析的源极电流的方法。 的方法来分析源电流的波形，并考虑的电荷重新分布在整个半导体集成电路的数字电路的，表达数字电路具有串联寄生电容SIGMA Cch中＆uarr＆（* nT）和SIGMA Cch中＆darr＆ （NT）被充电和连接在源极和接地线之间。 电容器串联在时间序列基础上的转换包括在所述数字电路栅极上的逻辑的动作的分布计算。 确定性采矿在数字电路中的源极电流的波形的分析模型由寄生电容器串联一对夫妇respectivement寄生阻抗ZD和源极线的ZG和接地线的连接得到。

    ANALOG CLOCK MODULE
    55.
    发明公开
    ANALOG CLOCK MODULE 有权
    模拟时钟模块

    公开(公告)号：EP1151312A1

    公开(公告)日：2001-11-07

    申请号：EP99953024.9

    申请日：1999-10-01

    申请人： TERADYNE, INC.

    发明人： GAGE, Robert, B.

    IPC分类号： G01R31/3167 ,  G01R31/30

    CPC分类号： G01R31/3167 ,  G01R31/2841 ,  G01R31/30 ,  G01R31/3191 ,  G01R31/31922 ,  H03L7/18 ,  H03L7/1806

    摘要： An analog clock apparatus is disclosed including a digital clock source for producing a digital waveform of a predetermined frequency and a direct-digital-synthesizer. The synthesizer has an input to receive the digital waveform and is operative to generate a resultant analog waveform. Prediction logic is coupled to the digital clock source and the synthesizer for determining the relative phase relationships between the digital waveform and the analog waveform. The prediction logic is responsive to a prediction clock having a clock frequency approximating that of said digital clock source.

    Circuit and method for testing a dithered analog-to-digital converter
    56.
    发明公开
    Circuit and method for testing a dithered analog-to-digital converter 失效
    Schaltung und Verfahren zum Testen eines Dithering-Analog-Digital-Konverters。

    公开(公告)号：EP0682265A1

    公开(公告)日：1995-11-15

    申请号：EP95302823.0

    申请日：1995-04-26

    申请人： AT&T Corp.

    发明人： Norsworthy, Steven Robert ,  Walden, Robert W. ,  Rich, David Arthur

    IPC分类号： G01R31/3167

    CPC分类号： H03M3/378 ,  H03M3/328 ,  H03M3/458

    摘要： A device (100) comprises an analog-to-digital converter (200), a digital signal processor (500), a digital dither signal generator (400), and a signal coupling device (300) adapted to selectively couple one of the dither signal generator (400) and the digital signal processor (500) to the signal path in the converter (200). A method of testing a dithered analog-to-digital converter (200) employing an M-bit digital dither signal generator (400), M being a positive integer, comprises the steps of: generating an M-bit, periodic signal, providing the generated signal to the dithered converter (200) at a point along the signal path of the dithered converter in place of the dither signal, and measuring the digital output signal produced by the converter (200).

    摘要翻译： 一种设备（100）包括模拟 - 数字转换器（200），数字信号处理器（500），数字抖动信号发生器（400）和信号耦合器件（300），适于选择性地耦合抖动 信号发生器（400）和数字信号处理器（500）连接到转换器（200）中的信号路径。 一种测试使用M位数字抖动信号发生器（400）的抖动模数转换器（200）的方法，M是正整数，包括以下步骤：产生M位周期信号， 在抖动信号的沿着信号路径的点处，将抖动信号发送到抖动转换器（200），并测量由转换器（200）产生的数字输出信号。

    TEST SYSTEM FOR DETECTING FAULTS IN MULTIPLE DEVICES OF THE SAME TYPE
    57.
    发明公开
    TEST SYSTEM FOR DETECTING FAULTS IN MULTIPLE DEVICES OF THE SAME TYPE 审中-公开

    公开(公告)号：EP4397983A1

    公开(公告)日：2024-07-10

    申请号：EP23213158.1

    申请日：2023-11-29

    申请人： NXP B.V.

    发明人： Schat, Jan-Peter ,  Wielage, Paul

    IPC分类号： G01R31/28 ,  G01R31/316 ,  G01R31/3167 ,  G01R31/317 ,  G01R31/3187

    CPC分类号： G01R31/287 ,  G01R31/3187 ,  G01R31/31724 ,  G01R31/316 ,  G01R31/3167

    摘要： Method and test system for testing a plurality of identical devices; the system comprising: a plurality of built-in self-test, BIST, devices; at least one processor; and at least one memory storing instructions that cause the test system at least to: randomly generate stimulus parameters; apply the generated stimulus parameters N times to the plurality of identical devices using the BIST devices; measure a response of the plurality of identical devices to the generated stimulus parameters to produce MxN response outputs, where M is a number of the plurality of identical devices; calculating a defect likelihood for a test set of the plurality of identical devices, a mean of the test set response outputs, a standard deviation of reference set response outputs, and a standard deviation of the test set response outputs; determine that the defect likelihood for the test set is greater than a first threshold value, wherein in such a case the steps are repeated to obtain updated data.

    MACHINE LEARNING FOR SYNCING MULTIPLE FPGA PORTS IN A QUANTUM SYSTEM
    59.
    发明公开
    MACHINE LEARNING FOR SYNCING MULTIPLE FPGA PORTS IN A QUANTUM SYSTEM 审中-公开

    公开(公告)号：EP4220204A1

    公开(公告)日：2023-08-02

    申请号：EP23153085.8

    申请日：2023-01-24

    申请人： Quantum Machines

    发明人： ZVI, Avishai ,  WEBER, Ori ,  OFEK, Nissim

    IPC分类号： G01R31/317 ,  G01R31/3167 ,  G06N10/00

    摘要： In a quantum computer, quantum algorithms are performed by a qubit interacting with multiple quantum control pulses. The quantum control pulses are electromagnetic RF signals that are generated digitally at baseband and sent, via asynchronous ports, to DACs that feed an RF upconversion circuit. For synchronization, each asynchronous port is coupled to a multi-tap delay line. The setting of the multi-tap delay line is determined by a function of the port's setup-and-hold time. This function is trained, via machine learning, to be applicable across a variety of ports.