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147 条记录 (耗时 0.025 秒)

    Apparatus and method for stabilizing the frequency of a clock signal generated by an on-chip clock generator
    61.
    发明公开
    Apparatus and method for stabilizing the frequency of a clock signal generated by an on-chip clock generator 失效
    装置和用于稳定的由一个电路集成的时钟发生器的时钟信号所产生的频率的方法。

    公开(公告)号：EP0163875A1

    公开(公告)日：1985-12-11

    申请号：EP85104679.7

    申请日：1985-04-19

    申请人： International Business Machines Corporation

    发明人： Dick, Carroll John

    IPC分类号： G06F1/04

    CPC分类号： G06F1/04

    摘要： @ For generating from a system clock a high frequency clock signal, the pulse generator has two consecutive delay lines (10a1, 10a3) and additional evaluating circuitry (10a4...10a12) to obtain the intermediate pulses in correct timing relationship with respect to the oroginal system clock pulses. Each of the consecutive system clock pulses propagates through the first (10a1) and into the second (10a3) delay line whose tap outputs are latched (11...L4) as delay indications when the next system clock pulse occurs. From tap outputs of the first delay line (PS, PN, PF) each system pulse can be obtained in several different time positions. The latched delay indications are evaluated in AND gates (10a6, 10a7, 10a8) to obtain three delay indicator signals (SLOW, NORM, FAST) of which only one is active. The delay indicator signals and the tap output signals of the first delay line are combined (10a9...10a12) to obtain an intermediate pulse that has a time position exactly between two consecutive system clock pulses.

    摘要翻译： 用于从系统时钟产生高频时钟信号，该脉冲发生器具有两个连续的延迟线（10A1，10A3）和另外的评估电路（10A4 ......10À12），以获得在正确的定时关系中的中间脉冲相对于所述oroginal 系统时钟脉冲。 每个连续系统时钟脉冲的传播通过第一（10A1）和成作为延迟指示第二（10A3）延迟线谁的抽头输出被锁存（11 ... L4）当下一个系统时钟脉冲的发生。 从第一延迟线的抽头输出（PS，PN，PF）每个系统的脉冲可以用几种不同的时间位置而获得。 锁存的延迟指示在评估与门（10A6，10A7，10A8），以获得三个延迟指示信号（SLOW，NORM，FAST），其中只有一个是活动的。 所述延迟指示信号和所述第一延迟线的抽头输出信号被组合（10a9 ...10À12），以获得在中间脉冲那样具有正好两个连续的系统时钟脉冲之间的时间位置。

    Data exchange flow control method and apparatus
    64.
    发明公开
    Data exchange flow control method and apparatus 失效
    Verfahren und Anordnung zur Steuerung des Flusses beim Datenaustausch。

    公开(公告)号：EP0137928A2

    公开(公告)日：1985-04-24

    申请号：EP84108713.3

    申请日：1984-07-24

    申请人： International Business Machines Corporation

    发明人： Sachs, Martin William ,  Snedaker, Mark Carl

    IPC分类号： H04L1/12

    CPC分类号： H04L5/1446

    摘要： When two transceivers (12,14) communicate with each other, the one transceiver may operate at a different internal speed with respect to the other transceiver. In addition, one transceiver may possess different buffering capabilities with respect to the other transceiver. As a result, when one transceiver attempts to communicate with the other transceiver, the more powerful transceiver may overload the other transceiver. This is avoided in the disclosed system and method in which, prior to the initiation of a data transmission, the two transceivers exchange count and rate information. Count information designates the maximum number of bytes of data which the transceiver can receive within a single data frame. Rate information designates the maximum rate at which the transceiver can receive data frames. When the exchange of count and rate information is completed, data transmission will take place using the smaller of the two counts, and the smaller of the two rates.

    摘要翻译： 当两个收发器（12,14）彼此通信时，一个收发器可以相对于另一个收发器以不同的内部速度工作。 此外，一个收发器可以具有相对于另一个收发器的不同缓冲能力。 因此，当一个收发器尝试与另一个收发器进行通信时，功能更强大的收发器可能使其他收发器过载。 这在所公开的系统和方法中是避免的，其中在数据传输开始之前，两个收发器交换计数和速率信息。 计数信息指定收发器在单个数据帧内可以接收的最大数据字节数。 速率信息指定收发器可以接收数据帧的最大速率。 当计数和费率信息的交换完成时，数据传输将使用两个计数中较小的一个，而两个比率中较小的一个。

    Improved multiplier architecture
    65.
    发明公开
    Improved multiplier architecture 失效
    Architektur eines Multiplizierers。

    公开(公告)号：EP0129039A1

    公开(公告)日：1984-12-27

    申请号：EP84105182.4

    申请日：1984-05-09

    申请人： International Business Machines Corporation

    发明人： Frey, Alexander H.

    IPC分类号： G06F7/49

    CPC分类号： G06F7/4824

    摘要： An improved multiplier is disclosed for multiplying a first operand times a second operand, which includes a Booth-type translator (22) having an input connected to receive the first operand (Y), for translating the binary expression of the first operand.into a sequence of signed digits. The multiplier further includes a partial product generator (30) having a first input connected to the output of the translator and a second input connected to receive the second operand (X), for multiplying the translated first operand times the second operand and furnishing partial products consisting of signed digits. The multiplier further includes an array of adders (36), each adder having having its inputs connected to two of the signed digit outputs from the partial product generator, for providing a sum consisting of a sequence of signed digits. The multiplier further includes an inverse translator (40) having an input connected to the output of the adders, for operating on the sequence of signed digits furnished by the adders, for providing a conventional binary expression for the product of the first and the second operands.

    摘要翻译： 公开了一种改进的乘法器，用于将第一操作数乘以第二操作数，第二操作数包括具有连接以输入第一操作数（Y）的输入的布斯类型转换器（22），用于将第一操作数的二进制表达式转换为序列 有符号数字。 所述乘法器还包括部分乘积发生器（30），其具有连接到所述转换器的输出端的第一输入端和连接以接收所述第二操作数（X）的第二输入端，用于将所述经翻译的第一操作数乘以所述第二操作数并提供部分乘积 由有符号数字组成。 乘法器还包括加法器阵列（36），每个加法器的输入连接到来自部分乘积产生器的两个有符号数字输出，用于提供由有符号数字序列组成的和。 乘法器还包括具有连接到加法器的输出的输入的反转换器（40），用于对由加法器提供的有符号数字序列进行操作，以提供用于第一和第二操作数的乘积的常规二进制表达式 。

    Method of producing field effect transistors having very short channel length
    70.
    发明公开
    Method of producing field effect transistors having very short channel length 失效
    一种生产具有非常短的沟道长度的场效应晶体管的制造方法。

    公开(公告)号：EP0083088A2

    公开(公告)日：1983-07-06

    申请号：EP82111969.0

    申请日：1982-12-27

    申请人： International Business Machines Corporation

    发明人： Riseman, Jacob ,  Tsang, Paul Ja-Min

    IPC分类号： H01L21/00 ,  H01L29/68 ,  H01L29/78

    CPC分类号： H01L29/66659 ,  H01L21/0337 ,  H01L21/2815 ,  H01L29/78 ,  Y10S438/942 ,  Y10S438/947

    摘要： Methods for producing field effect transistor devices having very short channel length are described. A surface isolation pattern (12) in a semiconductor substrate (10) isolates device regions of the semiconductor within the substrate from one another. An insulating layer (16) destined to be the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern (12). Then a first polycrystalline silicon layer (20) is formed thereover. A masking layer (22) such as silicon dioxide is then formed upon the first polycrystalline layer. The multilayer structure is etched to result in a patterned first polycrystalline silicon layer having substantially vertical sidewalls. A sub- micrometer thickness conductive layer (26') is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness conductive sidewall layer (26') portions of which extend across certain of the device regions. The sidewall conductive layer is utilized as the gate electrode of the field effect transistor devices.