公开(公告)号：EP3017666B1

公开(公告)日：2017-08-02

申请号：EP14738355.8

申请日：2014-06-23

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： SCHRITTWIESER, Wolfgang ,  MORIANZ, Mike ,  KASPER, Alexander ,  PREINER, Erich ,  KRIVEC, Thomas

IPC: H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K3/00 ,  H05K3/02 ,  H01L21/56

CPC classification number: H05K3/32 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/8203 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/185 ,  H05K3/0026 ,  H05K3/02 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/0574 ,  H05K2203/1469

公开(公告)号：EP1821587B1

公开(公告)日：2017-08-02

申请号：EP07002961.6

申请日：2007-02-12

Applicant: DENSO CORPORATION

Inventor： Ito, Atsushi ,  Honda, Takayoshi ,  Mikura, Hidehiro ,  Tsuruzawa, Tadashi ,  Sakuta, Takuya

IPC: H05K3/34

CPC classification number: H05K3/3421 ,  H05K1/111 ,  H05K3/3426 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09709 ,  H05K2201/10189 ,  H05K2201/10787 ,  Y02P70/611 ,  Y02P70/613

公开(公告)号：EP3075006A1

公开(公告)日：2016-10-05

申请号：EP14805471.1

申请日：2014-10-09

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： STAHR, Johannes ,  MORIANZ, Mike

IPC: H01L23/538 ,  H05K1/18

CPC classification number: H05K1/185 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/244 ,  H01L2224/2518 ,  H01L2224/8201 ,  H01L2224/82039 ,  H01L2224/82359 ,  H01L2224/82379 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/108 ,  H05K3/26 ,  H05K3/46 ,  H05K2201/09509 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2203/0392 ,  H05K2203/125

Abstract: The invention relates to a circuit board structure (21, 22), comprising at least one insulating layer (10), at least one conducting layer (11, 12), and at least one embedded component (1, 23 - 26) having contact pads (5) having an outer barrier layer (4), wherein at least two conducting tracks/conducting layers (19, 20) are connected to at least two connections (8; 8d, 8g, 8s) by means of vias (9; 9d, 9g, 9s) and each via (9; 9d, 9g, 9s) extends from a conducting track/conducting layer (11, 12) directly to the barrier contact layer (4; 4d, 4g, 4s) of the corresponding connection (8; 8d, 8g, 8s) of the component (1, 23 - 26).

Abstract translation: 一种印刷电路板结构，其包括至少一个绝缘层，至少一个导体层和至少一个具有接触焊盘的嵌入部件，所述接触焊盘具有外部阻挡层，其中至少两个导体路径/导体层的结构连接到 至少两个使用通孔的连接，并且每个通孔从导体路径/导体层直接连接到部件的对应连接的阻挡接触层。

公开(公告)号：EP2865787A1

公开(公告)日：2015-04-29

申请号：EP13189652.4

申请日：2013-10-22

Applicant: Atotech Deutschland GmbH

Inventor： Macioßek, Andreas ,  Mann, Olivier, Dr. ,  Cebulla, Pamela

IPC: C25D5/18 ,  C25D3/38 ,  C25D5/02 ,  H05K3/42 ,  C25D7/12

CPC classification number: C25D5/02 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/56 ,  C25D7/123 ,  C25D17/001 ,  C25D17/10 ,  C25D21/18 ,  H05K2201/09509

Abstract: The method for copper electroplating according to the present invention comprises an aqueous acidic copper plating bath and at least one reverse current pulse cycle consisting of one forward current pulse and one reverse current pulse wherein the fraction of the reverse charge to the forward charge applied to the substrate in said at least one current pulse cycle ranges between 0.1 to 5 %. The method is particularly suitable for simultaneously filling blind micro vias and plating trenches with a rectangular cross-sectional shape.

Abstract translation: 根据本发明的用于电镀铜的方法包括含水酸性镀铜浴和至少一个由一个正向电流脉冲和一个反向电流脉冲组成的反向电流脉冲周期，其中反向电荷与施加到 所述至少一个电流脉冲周期中的衬底的范围在0.1至5％之间。 该方法特别适用于同时填充具有矩形横截面形状的盲孔和电镀槽。

公开(公告)号：EP1461985B1

公开(公告)日：2014-10-22

申请号：EP03789847.5

申请日：2003-11-20

Applicant: Rockstar Consortium US LP

Inventor： KWONG, Herman ,  DIFILIPPO, Luigi ,  DUXBURY, Guy ,  MARCANTI, Larry

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/023 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10545 ,  H05K2201/10734

公开(公告)号：EP2077703B1

公开(公告)日：2013-08-21

申请号：EP09156862.6

申请日：2000-09-01

Applicant: IBIDEN CO., LTD.

Inventor： Inagaki, Yasushi ,  Asai, Motoo ,  Wang, Dongdong ,  Yabashi, Hideo ,  Shirai, Seiji

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

公开(公告)号：EP1243167B1

公开(公告)日：2013-04-10

申请号：EP00984002.6

申请日：2000-12-07

Applicant: Intel Corporation

Inventor： CHAKRAVORTY, Kishore ,  DORY, Thomas ,  GARNER, C., Michael

IPC: H05K1/16 ,  H01L23/64

CPC classification number: H05K1/162 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09809 ,  H05K2203/0315 ,  Y10T29/43

公开(公告)号：EP1895589A3

公开(公告)日：2013-04-03

申请号：EP07122506.4

申请日：1998-09-28

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo ,  Mori, Yoji

IPC: H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H01L23/50 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/114 ,  H05K1/116 ,  H05K3/3457 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The invention relates to a package board composed as a multi-layer wiring board, comprising a plurality of conductor circuits (158U,158D) formed in an outermost layer, an insulating layer (150) for supporting a plurality of said conductor circuits formed in said outermost layer and a plurality of inner layer conductor circuits formed under said insulating layer, wherein a plurality of said inner layer conductor circuits are a power supply layer (58U) and/or a ground layer (58D), a soldering bump (76U,76D) is formed, through said insulting layer, on each via-hole (160U,160D) connected to an inner layer conductor circuit.

Abstract translation: 本发明涉及一种构成为多层布线板的封装板，包括形成在最外层中的多个导体电路（158U，158D），用于支撑形成在所述多层布线板中的多个所述导体电路的绝缘层（150） 最外层和形成在所述绝缘层下面的多个内层导体电路，其中多个所述内层导体电路是电源层（58U）和/或接地层（58D），焊接凸点（76U，76D ）通过所述绝缘层形成在连接到内层导体电路的每个通孔（160U，160D）上。

公开(公告)号：EP1895587A3

公开(公告)日：2013-04-03

申请号：EP07122509.8

申请日：1998-09-28

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo ,  Mori, Yoji

IPC: H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H01L23/50 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/114 ,  H05K1/116 ,  H05K3/3457 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The invention relates to a package board having a core board with a conductor layer formed on each surface, another conductor layer formed on said conductor layer with an interlaminar resin insulating layer therebetween, and a conductor layer on either of said surfaces of said core board being used as an electrode layer, wherein the land (41a) of a through-hole of said core board, disposed in a conductor layer formed as said electrode layer, is united with a pad (41b) connected to a via-hole formed through an interlaminar resin insulating layer formed on the top surface of said package board.

公开(公告)号：EP2290753B1

公开(公告)日：2012-12-05

申请号：EP09011143.6

申请日：2009-08-31

Applicant: ERNI Electronics GmbH

Inventor： Lappöhn, Jürgen

IPC: H05K1/02 ,  H01R12/72

CPC classification number: H01R12/727 ,  H01R13/658 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/308 ,  H05K3/3426 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10189