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    MISMATCH CALIBRATION OF CAPACITIVE DIFFERENTIAL ISOLATOR
    61.
    发明公开
    MISMATCH CALIBRATION OF CAPACITIVE DIFFERENTIAL ISOLATOR 审中-公开
    FEHLANPASSUNGSKALIBRIERUNG EINES KAPAZITIVEN DIFFERENTIELLEN ISOLATORS

    公开(公告)号：EP3163823A1

    公开(公告)日：2017-05-03

    申请号：EP16193379

    申请日：2016-10-11

    申请人： ANALOG DEVICES INC

    发明人： HA DONGWAN

    IPC分类号： H04L25/02

    CPC分类号： H03H11/28 ,  H03H11/04 ,  H03K3/012 ,  H03K19/018521 ,  H04L25/0278 ,  H04L25/12

    摘要： Embodiments of the present disclosure may provide a method of calibrating an isolator system. The method may comprise the steps of driving a common signal to a pair of input terminals of the isolator system; measuring differences in signals at output terminals of the isolator system; and varying impedance of impedance elements connected between the output terminals and a center-tap terminal of the isolator system until a mismatch at the output terminals is minimized.

    摘要翻译： 本公开的实施例可以提供一种校准隔离器系统的方法。 该方法可以包括以下步骤：将公共信号驱动到隔离器系统的一对输入端子; 测量隔离器系统输出端信号的差异; 以及改变连接在隔离器系统的输出端子和中心抽头端子之间的阻抗元件的阻抗，直到输出端子处的失配被最小化。

    LIMITING AGING EFFECTS IN ANALOG DIFFERENTIAL CIRCUITS
    65.
    发明公开
    LIMITING AGING EFFECTS IN ANALOG DIFFERENTIAL CIRCUITS 审中-公开
    BEGRENZUNG VON ALTERUNGSAUSWIRKUNGEN IN ANALOGEN DIFFERENZSCHALTUNGEN

    公开(公告)号：EP3070485A3

    公开(公告)日：2016-11-09

    申请号：EP16158456.0

    申请日：2016-03-03

    申请人： Analog Devices, Inc.

    发明人： FERGUSON, Paul F. ,  MANGANARO, Gabriele

    IPC分类号： G01R31/26 ,  G01R31/28 ,  H03M1/06 ,  H03M1/12

    摘要： Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.

    摘要翻译： 使用深纳米互补金属氧化物半导体（CMOS）工艺制造的器件的老化效应可能导致电路随时间呈现出不期望的不匹配积累。 为了解决老化效应，控制到一组M个差分电路的连接，以限制和系统地最小化或逆转老化效应。 在一个实施例中，选择控制置换序列以在至少两个不同时间段期间在相反的应力条件下对M个差分电路的阵列施加应力。 施加相反的应力条件，优选地基本上相等的相反的应力条件可以反转不匹配积累的方向，并且在可接受的限度内限制不匹配的积累。 控制置换序列可以应用于模数转换器的比较器阵列，或折叠模数转换器的差分放大器阵列。

    LIMITING AGING EFFECTS IN ANALOG DIFFERENTIAL CIRCUITS
    66.
    发明公开
    LIMITING AGING EFFECTS IN ANALOG DIFFERENTIAL CIRCUITS 审中-公开
    模拟微分电路中限制老化效应

    公开(公告)号：EP3070485A2

    公开(公告)日：2016-09-21

    申请号：EP16158456.0

    申请日：2016-03-03

    申请人： Analog Devices, Inc.

    发明人： FERGUSON, Paul F. ,  MANGANARO, Gabriele

    IPC分类号： G01R31/26

    摘要： Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.

    摘要翻译： 使用深纳米互补金属氧化物半导体（CMOS）工艺制造的器件的老化效应会导致电路随着时间的推移表现出不期望的失配累积。 为了解决老化效应，控制与M个微分电路阵列的连接以限制并系统地最小化或逆转老化效应。 在一个实施例中，选择控制置换序列以在至少两个不同时间段期间在相反的应力条件下对M个差分电路的阵列施加应力。 施加相反的应力条件，优选基本相等的相反应力条件，可以颠倒失配累积的方向并将失配累积限制在可接受的限度内随时间推移。 控制置换序列可以应用于模数转换器的比较器阵列或折叠模数转换器的差分放大器阵列。

    SYSTEM LINEARIZATION
    67.
    发明公开
    SYSTEM LINEARIZATION 审中-公开
    SYSTEMLINEARISIERUNG

    公开(公告)号：EP3054590A1

    公开(公告)日：2016-08-10

    申请号：EP16150791.8

    申请日：2012-11-16

    申请人： Analog Devices, Inc.

    发明人： WEBER, Theophane ,  VIGODA, Benjamin ,  PRATT, Patrick ,  PARK, Joshua

    IPC分类号： H03F1/32

    CPC分类号： H03F1/3247 ,  H03F1/3258 ,  H03F1/3282 ,  H03F2201/3209 ,  H03F2201/3224

    摘要： A method for linearizing a non-linear system element includes acquiring data representing inputs and corresponding outputs of the non-linear system element. A model parameter estimation procedure is applied to the acquired data to determine model parameters of a model characterizing input-output characteristics of the non-linear element. An input signal representing a desired output signal of the non-linear element is accepted and processed to form a modified input signal according to the determined model parameters. The processing includes, for each of a series of successive samples of the input signal, applying an iterative procedure to determining a sample of the modified input signal according to a predicted output of the model of the non-linear element. The modified input signal is provided for application to the input of the non-linear element.

    摘要翻译： 线性化非线性系统元件的方法包括获取表示非线性系统元件的输入和相应输出的数据。 将模型参数估计程序应用于所获取的数据，以确定表征非线性元素的输入 - 输出特性的模型的模型参数。 接收并处理表示非线性元件的期望输出信号的输入信号，以根据确定的模型参数来形成修改的输入信号。 该处理包括对于输入信号的一系列连续采样中的每一个，根据非线性元件的模型的预测输出，应用迭代过程来确定经修改的输入信号的采样。 修改后的输入信号用于应用于非线性元件的输入。

    APPARATUS AND METHODS FOR CLOCK AND DATA RECOVERY
    68.
    发明公开
    APPARATUS AND METHODS FOR CLOCK AND DATA RECOVERY 有权
    用于时钟和数据恢复的装置和方法

    公开(公告)号：EP3043477A2

    公开(公告)日：2016-07-13

    申请号：EP16150636.5

    申请日：2016-01-08

    申请人： Analog Devices, Inc.

    发明人： McCRACKEN, Stuart ,  KENNEY, John ,  TAM, Kimo

    IPC分类号： H03L7/091 ,  H04L7/033 ,  H04L25/14

    CPC分类号： H04L7/0337 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H04L7/0008 ,  H04L7/002 ,  H04L7/0033 ,  H04L7/02 ,  H04L7/042 ,  H04L25/14

    摘要： Apparatus and methods for clock and data recovery (CDR) are provided herein. In certain configurations, a first CDR circuit captures data and edge samples from a first input data stream received over a first lane. The data and edge samples are used to generate a master phase signal, which is used to control a phase of a first data sampling clock signal used for capturing the data samples. Additionally, the first CDR circuit generates a master phase error signal based on changes to the master phase signal over time, and forwards the master phase error signal to at least a second CDR circuit. The second CDR circuit processes the master phase error signal to generate a slave phase signal used to control a phase of a second data sampling clock signal used for capturing data samples from a second input data stream received over a second lane.

    摘要翻译： 本文提供了用于时钟和数据恢复（CDR）的装置和方法。 在某些配置中，第一CDR电路从通过第一通道接收的第一输入数据流捕获数据和边缘采样。 数据和边缘采样用于产生主相位信号，该主相位信号用于控制用于采集数据采样的第一数据采样时钟信号的相位。 另外，第一CDR电路基于主时钟信号随时间的变化产生主相位误差信号，并且将主相位误差信号转发到至少第二CDR电路。 第二CDR电路处理主相位误差信号以生成用于控制用于从第二通道上接收到的第二输入数据流捕捉数据样本的第二数据采样时钟信号的相位的从相位信号。