公开(公告)号：EP0391404A1

公开(公告)日：1990-10-10

申请号：EP90106502.9

申请日：1990-04-05

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Takatori, Sunao ,  Kumagai, Ryohei ,  Yamamoto, Makoto ,  Matsumoto, Koji

IPC分类号： G06F15/76

CPC分类号： G06N3/04

摘要： A data processing system having a neural layer which comprises a neuron for comparing a sum of inputted data weighted by a weight with a threshold so as to output an output according to a result of the comparing, characterized in that the neural layer comprises as many neural layers as a difference between an abstraction degree of input and output data of the data processing system.

摘要翻译： 一种具有神经层的数据处理系统，所述神经层包括用于将通过权重加权的输入数据的和与阈值进行比较以根据比较结果输出输出的神经元，其特征在于所述神经层包括与神经元一样多的神经 层作为数据处理系统的输入和输出数据的抽象程度之间的差异。

公开(公告)号：EP0757450B1

公开(公告)日：2004-10-06

申请号：EP96112313.0

申请日：1996-07-30

申请人： Yozan, Inc. ,  SHARP KABUSHIKI KAISHA

发明人： Zhou, Changming ,  Shou, Guoliang ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： H04B1/707

CPC分类号： H04B1/708 ,  H04B1/7085 ,  H04B1/7093 ,  H04B1/7095 ,  H04B2201/70709

公开(公告)号：EP0838910A3

公开(公告)日：2003-03-19

申请号：EP97118371.0

申请日：1997-10-22

申请人： NTT DoCoMo, Inc. ,  Yozan, Inc.

发明人： Shou, Guoliang ,  Zhou, Changming ,  Zhou, Xuping ,  Yamamoto, Makoto ,  Takatori, Sunao ,  Sawahashi, Mamoru ,  Adachi, Fumiyuki

IPC分类号： H04B1/707 ,  H04Q7/38

CPC分类号： H04W48/18 ,  H04B1/70735 ,  H04B1/70775 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7093 ,  H04B1/7117 ,  H04B2201/70702 ,  H04W36/00

摘要： The present invention realizes a rapid and efficient cell search and small-size instrument for an asynchronous DS-CDMA cellular system. This cell search detects the correlation between the received signal and the short code of the control channel, and matched filter 22 detects the maximum electric power correlation peak location. Next, using correlators 28-1 to 28-n which are parallelly set in a plurality for RAKE processing with plurality, identifies the long code that is set in the system with the detected long code timing. After the long code is synchronized, a multipath signal is received using 28-1 to 28-n, and the data is judged by RAKE processing. When peripheral cell search is executed, after long code timing is detected by using matched filter 22, the long code of the candidate peripheral cell is designated using the same matched filter. Handover is safely realized by receiving the signal from the connected base station by correlators 28-1 to 28-n, and the base station signal through handover by 22.

公开(公告)号：EP0756377B1

公开(公告)日：2001-10-24

申请号：EP96111795.9

申请日：1996-07-22

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Zhou, Changming ,  Motohashi, Kazunori ,  Quin, Xiaoling ,  Lin, Shengmin ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： H03H11/04 ,  H03H17/02

CPC分类号： H04B1/7093 ,  H03H11/04 ,  H03H17/0254 ,  H04B1/7117

公开(公告)号：EP0810741A3

公开(公告)日：2001-09-12

申请号：EP97108514.7

申请日：1997-05-27

申请人： YOZAN INC.

发明人： Shou, Gouliang ,  Zhou, Changming ,  Zhou, Xuping ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： H04B1/707

CPC分类号： H04B1/708 ,  H04B1/7093 ,  H04B1/7115 ,  H04B2201/70709

摘要： This invention reduces electric power consumption of a CDMA communication system receiver in the wait mode. The received spread spectrum signal is demodulated in multiplication means 16 and 17 into baseband signals Ri and Rq, and input in complex matched filter 22. This filter is intermittently driven by supply voltage control means 20 to perform acquisition of received signals. When electric power calculation circuit 23 detects that outputs of this filter have a peak equal to or greater than a predetermined value, the received signals undergo acquisition by controlling n number of correlators 26-1 to 26-n to work by correlator controlling circuit 25; moreover, de-spreading is performed. Outputs from each correlator 26-1 to 26-n are given to RAKE combiner and demodulated by RAKE combining and demodulating circuit 28.

公开(公告)号：EP0790712A3

公开(公告)日：1999-02-24

申请号：EP97102710.7

申请日：1997-02-19

申请人： YOZAN INC. ,  KOKUSAI ELECTRIC CO., LTD.

发明人： Zhou, Changming ,  Shou, Guoliang ,  Zhou, Xuping ,  Yamamoto, Makoto ,  Urabe, Kenzo ,  Takatori, Suano

IPC分类号： H04B1/707

CPC分类号： H04B1/7093

摘要： The demodulator has a plurality of matched filters in parallel. Each matched filter has a different binary PN code, a plurality of sample holders, a plurality of multipliers, an adder, and a controller. The sample holders has a common input, a switch, a first capacitor, a first inverse amplifier with an output and an input connected to the common input through the switch and the capacitor, and a first feedback capacitor for feeding the output of the first inverse amplifier back to the input. Each multiplier has a first and second sub-multiplexers, one of sub-multiplexer selecting corresponding sample holder output and another sub-multiplexer selecting a reference voltage.

摘要翻译： 解调器具有多个并联的匹配滤波器。 每个匹配滤波器具有不同的二进制PN码，多个样本保持器，多个乘法器，加法器和控制器。 样本保持器具有公共输入端，开关，第一电容器，具有输出端的第一反向放大器和通过开关和电容器连接到公共输入端的输入端，以及用于馈送第一反相输出端的第一反馈电容器 放大器返回到输入。 每个乘法器具有第一和第二子多路复用器，其中一个子多路复用器选择相应的样本保持器输出，另一个子多路复用器选择参考电压。

公开(公告)号：EP0838910A2

公开(公告)日：1998-04-29

申请号：EP97118371.0

申请日：1997-10-22

申请人： NTT MOBILE COMMUNICATIONS NETWORK INC. ,  YOZAN INC.

发明人： Shou, Guoliang ,  Zhou, Changming ,  Zhou, Xuping ,  Yamamoto, Makoto ,  Takatori, Sunao ,  Sawahashi, Mamoru ,  Adachi, Fumiyuki

IPC分类号： H04B1/707 ,  H04Q7/38

CPC分类号： H04W48/18 ,  H04B1/70735 ,  H04B1/70775 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7093 ,  H04B1/7117 ,  H04B2201/70702 ,  H04W36/00

摘要： The present invention realizes a rapid and efficient cell search and small-size instrument for an asynchronous DS-CDMA cellular system. This cell search detects the correlation between the received signal and the short code of the control channel, and matched filter 22 detects the maximum electric power correlation peak location. Next, using correlators 28-1 to 28-n which are parallelly set in a plurality for RAKE processing with plurality, identifies the long code that is set in the system with the detected long code timing. After the long code is synchronized, a multipath signal is received using 28-1 to 28-n, and the data is judged by RAKE processing. When peripheral cell search is executed, after long code timing is detected by using matched filter 22, the long code of the candidate peripheral cell is designated using the same matched filter. Handover is safely realized by receiving the signal from the connected base station by correlators 28-1 to 28-n, and the base station signal through handover by 22.

摘要翻译： 本发明实现了用于异步DS-CDMA蜂窝系统的快速且有效的小区搜索和小尺寸仪器。 该小区搜索检测接收信号与控制信道的短码之间的相关性，匹配滤波器22检测最大功率相关峰值位置。 接下来，使用多个并行设置为用于RAKE处理的多个的相关器28-1至28-n识别具有检测到的长码定时的系统中设置的长码。 在长代码同步之后，使用28-1至28-n接收多路径信号，并且通过RAKE处理来判断数据。 当执行外围小区搜索时，通过使用匹配滤波器22检测长代码定时之后，使用相同的匹配滤波器来指定候选周边小区的长码。 通过相关器28-1至28-n接收来自所连接的基站的信号，以及通过22切换的基站信号来安全地实现切换。

公开(公告)号：EP0405174B1

公开(公告)日：1998-03-11

申请号：EP90110384.6

申请日：1990-05-31

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Takatori, Sunao ,  Kumagai, Ryohei ,  Yamamoto, Makoto ,  Matsumoto, Koji

IPC分类号： G06F15/80

CPC分类号： G06N3/08

公开(公告)号：EP0825545A1

公开(公告)日：1998-02-25

申请号：EP97113678.3

申请日：1997-08-07

申请人： YOZAN INC.

发明人： Zhou, Changming ,  Shou, Guoliang ,  Suzuki, Kunihiko ,  Motohashi, Kazunori ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： G06G7/22

CPC分类号： G06G7/22

摘要： The present invention provides a highly accurate vector absolute-value calculation circuit using analog processing and minimal hardware. Signal voltages corresponding to component I (real number part) and component Q (imaginary number part) are input to the first absolute-value calculation circuit 13 and the second absolute-value calculation circuit 14 from terminals 11 and 12, respectively, and they are each converted into absolute-value signals. The component I absolute-value and component Q absolute-value are compared in comparison circuit 20. According to the result, the larger absolute-value signals are output to input capacitor 23 of a neural computation circuit, and the smaller absolute-value signals are output to input capacitor 24 by controlling multiplexers 21 and 22. The capacity ratio of feedback capacitor 26 of a neural computation circuit and input capacitors 23 and 24 is 11:10:5. The complex number absolute-value calculated by the following formula is output from output terminal 27. Mag = 10 11 Max { Abs ( I ), Abs ( Q )} + 5 11 Min { Abs ( I ), Abs ( Q )}

摘要翻译： 本发明提供了一种使用模拟处理和最少硬件的高精度矢量绝对值计算电路。 对应于分量I（实数部分）和分量Q（虚数部分）的信号电压分别从端子11和12输入到第一绝对值计算电路13和第二绝对值计算电路14，并且它们是 每个转换成绝对值信号。 在比较电路20中比较分量I绝对值和分量Q绝对值。根据结果，较大的绝对值信号被输出到神经计算电路的输入电容器23，并且较小的绝对值信号是 通过控制多路复用器21和22输出到输入电容器24.神经计算电路的反馈电容器26与输入电容器23和24的电容比是11：10：5。 从输出端子27输出由下式算出的复数绝对值.Mag = 1011Max {Abs（I），Abs（Q）} + 511Min {Abs（I），Abs（Q）}

公开(公告)号：EP0810741A2

公开(公告)日：1997-12-03

申请号：EP97108514.7

申请日：1997-05-27

申请人： YOZAN INC.

发明人： Shou, Gouliang ,  Zhou, Changming ,  Zhou, Xuping ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： H04B1/707

CPC分类号： H04B1/708 ,  H04B1/7093 ,  H04B1/7115 ,  H04B2201/70709

摘要： This invention reduces electric power consumption of a CDMA communication system receiver in the wait mode. The received spread spectrum signal is demodulated in multiplication means 16 and 17 into baseband signals Ri and Rq, and input in complex matched filter 22. This filter is intermittently driven by supply voltage control means 20 to perform acquisition of received signals. When electric power calculation circuit 23 detects that outputs of this filter have a peak equal to or greater than a predetermined value, the received signals undergo acquisition by controlling n number of correlators 26-1 to 26-n to work by correlator controlling circuit 25; moreover, de-spreading is performed. Outputs from each correlator 26-1 to 26-n are given to RAKE combiner and demodulated by RAKE combining and demodulating circuit 28.

摘要翻译： 本发明降低了等待模式下CDMA通信系统接收机的电力消耗。 接收的扩频信号在乘法装置16和17中被解调成基带信号Ri和Rq，并输入复合匹配滤波器22.该滤波器由电源电压控制装置20间歇地驱动，以执行接收信号的获取。 当电力计算电路23检测到该滤波器的输出具有等于或大于预定值的峰值时，通过控制n个相关器26-1至26-n以由相关器控制电路25进行工作来对所接收的信号进行采集; 此外，执行解扩。 来自每个相关器26-1至26-n的输出被提供给RAKE组合器并由RAKE组合和解调电路28解调。