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78 条记录 (耗时 0.014 秒)

    Vector absolute-value calculation circuit
    61.
    发明公开
    Vector absolute-value calculation circuit 失效
    矢量绝对值计算电路

    公开(公告)号：EP0825545A1

    公开(公告)日：1998-02-25

    申请号：EP97113678.3

    申请日：1997-08-07

    申请人： YOZAN INC.

    发明人： Zhou, Changming ,  Shou, Guoliang ,  Suzuki, Kunihiko ,  Motohashi, Kazunori ,  Yamamoto, Makoto ,  Takatori, Sunao

    IPC分类号： G06G7/22

    CPC分类号： G06G7/22

    摘要： The present invention provides a highly accurate vector absolute-value calculation circuit using analog processing and minimal hardware. Signal voltages corresponding to component I (real number part) and component Q (imaginary number part) are input to the first absolute-value calculation circuit 13 and the second absolute-value calculation circuit 14 from terminals 11 and 12, respectively, and they are each converted into absolute-value signals. The component I absolute-value and component Q absolute-value are compared in comparison circuit 20. According to the result, the larger absolute-value signals are output to input capacitor 23 of a neural computation circuit, and the smaller absolute-value signals are output to input capacitor 24 by controlling multiplexers 21 and 22. The capacity ratio of feedback capacitor 26 of a neural computation circuit and input capacitors 23 and 24 is 11:10:5. The complex number absolute-value calculated by the following formula is output from output terminal 27. Mag = 10 11 Max { Abs ( I ), Abs ( Q )} + 5 11 Min { Abs ( I ), Abs ( Q )}

    摘要翻译： 本发明提供了一种使用模拟处理和最少硬件的高精度矢量绝对值计算电路。 对应于分量I（实数部分）和分量Q（虚数部分）的信号电压分别从端子11和12输入到第一绝对值计算电路13和第二绝对值计算电路14，并且它们是 每个转换成绝对值信号。 在比较电路20中比较分量I绝对值和分量Q绝对值。根据结果，较大的绝对值信号被输出到神经计算电路的输入电容器23，并且较小的绝对值信号是 通过控制多路复用器21和22输出到输入电容器24.神经计算电路的反馈电容器26与输入电容器23和24的电容比是11：10：5。 从输出端子27输出由下式算出的复数绝对值.Mag = 1011Max {Abs（I），Abs（Q）} + 511Min {Abs（I），Abs（Q）}

    Receiver for code division multiple access communication system
    62.
    发明公开
    Receiver for code division multiple access communication system 失效
    接收器用于码分多址通信系统

    公开(公告)号：EP0810741A2

    公开(公告)日：1997-12-03

    申请号：EP97108514.7

    申请日：1997-05-27

    申请人： YOZAN INC.

    发明人： Shou, Gouliang ,  Zhou, Changming ,  Zhou, Xuping ,  Yamamoto, Makoto ,  Takatori, Sunao

    IPC分类号： H04B1/707

    CPC分类号： H04B1/708 ,  H04B1/7093 ,  H04B1/7115 ,  H04B2201/70709

    摘要： This invention reduces electric power consumption of a CDMA communication system receiver in the wait mode. The received spread spectrum signal is demodulated in multiplication means 16 and 17 into baseband signals Ri and Rq, and input in complex matched filter 22. This filter is intermittently driven by supply voltage control means 20 to perform acquisition of received signals. When electric power calculation circuit 23 detects that outputs of this filter have a peak equal to or greater than a predetermined value, the received signals undergo acquisition by controlling n number of correlators 26-1 to 26-n to work by correlator controlling circuit 25; moreover, de-spreading is performed. Outputs from each correlator 26-1 to 26-n are given to RAKE combiner and demodulated by RAKE combining and demodulating circuit 28.

    摘要翻译： 本发明降低了等待模式下CDMA通信系统接收机的电力消耗。 接收的扩频信号在乘法装置16和17中被解调成基带信号Ri和Rq，并输入复合匹配滤波器22.该滤波器由电源电压控制装置20间歇地驱动，以执行接收信号的获取。 当电力计算电路23检测到该滤波器的输出具有等于或大于预定值的峰值时，通过控制n个相关器26-1至26-n以由相关器控制电路25进行工作来对所接收的信号进行采集; 此外，执行解扩。 来自每个相关器26-1至26-n的输出被提供给RAKE组合器并由RAKE组合和解调电路28解调。

    A/D converting circuit
    63.
    发明公开
    A/D converting circuit 失效
    Schaltung zur A / D-Wandlung

    公开(公告)号：EP0763897A2

    公开(公告)日：1997-03-19

    申请号：EP96114838.4

    申请日：1996-09-16

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Motohashi, Kazunori ,  Shou, Guoliang ,  Yamamoto, Makoto ,  Takatori, Sunao

    IPC分类号： H03M1/06

    CPC分类号： H03M1/168 ,  H03M1/804

    摘要： The present invention has an object to provide an A/D converting circuit with improved accuracy in an output. In this invention, the initial electric charge is given to a capacitive coupling for outputting in a quantizing circuit so as to cancel the dispersion of thresholds of MOS inverter in the quantizing circuit, the supply voltage of the first and the second inverters is higher than the supply voltage of an inverter for quantizing, as well as the initial electric charge is given to a capacitance for input in order to limit the function of the quantizing circuit within the linear area of the first and the second inverters.

    摘要翻译： 本发明的目的是提供一种具有提高的输出精度的A / D转换电路。 在本发明中，初始电荷被赋予用于在量化电路中输出的电容耦合，以消除量化电路中MOS反相器的阈值的偏差，第一和第二反相器的电源电压高于 用于量化的逆变器的电源电压以及初始电荷被赋予用于输入的电容，以便限制第一和第二逆变器的线性区域内的量化电路的功能。

    Matched filter circuit
    65.
    发明公开
    Matched filter circuit 失效
    匹配滤波器电路

    公开(公告)号：EP0756378A1

    公开(公告)日：1997-01-29

    申请号：EP96112146.4

    申请日：1996-07-26

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Shou, Guoliang ,  Zhou, Changming ,  Yamamoto, Makoto ,  Takatori, Sunao

    IPC分类号： H03H11/04 ,  H03H17/02

    CPC分类号： H03H11/04 ,  H03H17/0254

    摘要： The present invention has an object to provide a matched filter with further reduced electric power. In a matched filter circuit according to the present invention, the electric power supply is stopped with respect to an unnecessary circuit according to an experience that signal is partially sampled just after the acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups"1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.

    摘要翻译： 本发明的目的在于提供一种功率进一步降低的匹配滤波器。 在根据本发明的匹配滤波器电路中，根据在采集之后信号被部分采样的经验，电力供应相对于不必要的电路停止。 由于扩展码是1位数据串，所以采样和保持的输入信号被多路复用器分支到信号组“1”和“-1”。 每组中的信号通过电容耦合并联添加，并且间歇地在电路中供应电力。

    Matched filter circuit
    66.
    发明公开
    Matched filter circuit 失效
    匹配滤波器电路

    公开(公告)号：EP0756377A1

    公开(公告)日：1997-01-29

    申请号：EP96111795.9

    申请日：1996-07-22

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Shou, Guoliang ,  Zhou, Changming ,  Motohashi, Kazunori ,  Quin, Xiaoling ,  Lin, Shengmin ,  Yamamoto, Makoto ,  Takatori, Sunao

    IPC分类号： H03H11/04 ,  H03H17/02

    CPC分类号： H04B1/7093 ,  H03H11/04 ,  H03H17/0254 ,  H04B1/7117

    摘要： An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "- 1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.

    摘要翻译： 本发明的一个目的是提供一种小尺寸和消耗低功率的匹配滤波器电路。 注意扩展码是1位数据串，输入信号被采样并作为沿时间序列的模拟信号被保持，被分类为“1”和“ - 1”，并且通过电容耦合将分类的信号并行地相加 在根据本发明的匹配滤波器电路中。