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    WIDE BAND MODULATION PLL AND MODULATION FACTOR ADJUSTMENT METHOD THEREOF
    62.
    发明公开
    WIDE BAND MODULATION PLL AND MODULATION FACTOR ADJUSTMENT METHOD THEREOF 审中-公开
    宽带调制PLL，AND METHOD FOR调整系数调制THEREOF

    公开(公告)号：EP1657812A4

    公开(公告)日：2009-01-21

    申请号：EP04748041

    申请日：2004-07-22

    申请人： PANASONIC CORP

    发明人： OCHI TAKETOSHI ,  HIRANO SHUNSUKE

    IPC分类号： H03C3/00 ,  H03C3/09 ,  H03L7/099 ,  H03L7/18 ,  H03L7/197

    CPC分类号： H03C3/0991 ,  H03C3/0916 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03L7/099 ,  H03L7/197 ,  H03L2207/06

    摘要： A broadband modulation PLL having an excellent modulation accuracy is provided at a low cost. A PLL includes a VCO (21), a frequency divider (22), a phase comparator (23), a charge pump (24) and a loop filter (25). The frequency division ratio of the frequency divider (22) and the VCO (21) are controlled for adjustment. The VCO (21) has two control terminals for PLL and for modulation. A control signal producing part (28) produces, based on an input voltage (Vt1) to be applied to the PLL control terminal and a phase modulation data, a control voltage (Vtm) to be applied to the VCO (21). During a modulation factor adjustment, the control voltage (Vtm) to be applied to the modulation control terminal of the VCO (21) is controlled, and the input voltage (Vt1) is measured to calculate the frequency modulation sensitivity of the VCO (21) to the control voltage (Vtm). Then, the modulation factor of the phase modulation data is adjusted based on the modulation sensitivity as calculated.

    Radio communications apparatus
    66.
    发明公开
    Radio communications apparatus 审中-公开
    Funknachrichtengerät

    公开(公告)号：EP1168648A3

    公开(公告)日：2004-12-15

    申请号：EP01115475.4

    申请日：2001-06-27

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Kojima, Noriharu ,  Watanabe, Hideki ,  Akaoka, Yasunobu ,  Takada, Junichi

    IPC分类号： H04B1/40

    CPC分类号： H03C3/0966 ,  H03D7/165 ,  H03L7/16 ,  H03L2207/12 ,  H04B1/403

    摘要： A phase comparator (106) compares a phase of the output signal of the quadrature modulator (104) with the phase of the signal obtained by frequency-converting the output signal of a first VCO (101) via the second VCO (102) and the first mixer (108). A PLL modulator includes a low-pass filter (107) filters a component below a predetermined frequency of the output signal of the phase comparator (106) and supplying the resulting signal to the frequency control terminal of the first VCO (101). The output signal (TS1) of the first VCO (101) is a modulated signal conforming to a modulation system having a constant envelope waveform, while the output signal of the quadrature modulator (104) is input to the first band-pass filter (110) and the output signal (TS2) of the first band-pass filter is a modulated signal conforming to a modulation system accompanied by an amplitude component as information.

    摘要翻译： 相位比较器（106）将正交调制器（104）的输出信号的相位与通过经由第二VCO（102）对第一VCO（101）的输出信号进行频率转换而获得的信号的相位进行比较， 第一混合器（108）。 PLL调制器包括低通滤波器（107）对低于相位比较器（106）的输出信号的预定频率的分量进行滤波，并将得到的信号提供给第一VCO（101）的频率控制端。 第一VCO（101）的输出信号（TS1）是符合具有恒定包络波形的调制系统的调制信号，而正交调制器（104）的输出信号被输入到第一带通滤波器 ），并且第一带通滤波器的输出信号（TS2）是符合伴随着振幅分量的调制系统作为信息的调制信号。

    Chaîne d'émission réception et procédé d'émission
    67.
    发明公开
    Chaîne d'émission réception et procédé d'émission 有权
    Sende-Empfängerund Verfahren

    公开(公告)号：EP1482635A2

    公开(公告)日：2004-12-01

    申请号：EP04018081.2

    申请日：1999-06-10

    申请人： ALCATEL

    发明人： Yang, Fuji ,  Genest, Pierre ,  Dussauby, Eric ,  Berland, Corinne ,  Maecker, Arnaud

    IPC分类号： H03C3/09

    CPC分类号： H03C3/0925 ,  H03C3/0966 ,  H03D7/163 ,  H03L7/16 ,  H03L7/23

    摘要： Une chaîne d'émission réception comporte une boucle (1) à verrouillage de phase et une boucle (2) à fréquence de translation. Pour provoquer des sauts de fréquence, on fait varier avec des grands (Ns, Ms) pas, mais en sens contraire, les fréquences dans les deux boucles. On montre que le bruit provoqué par la division en fréquence dans les boucles en est réduit.

    摘要翻译： 该通道具有分别用于产生中间，平移和传输频率信号的三个锁相环（1,2,3）。 环路（2）被分成两个，用于各个发送和接收电路。 每个平移回路具有压控振荡器，分频器，相位比较器和通带滤波器。

    VERFAHREN UND EINRICHTUNG ZUM ERZEUGEN VON MOBILFUNKSIGNALEN
    68.
    发明公开
    VERFAHREN UND EINRICHTUNG ZUM ERZEUGEN VON MOBILFUNKSIGNALEN 审中-公开
    方法和装置于产生移动SIGNALS

    公开(公告)号：EP1405418A2

    公开(公告)日：2004-04-07

    申请号：EP02745084.0

    申请日：2002-05-23

    申请人： Siemens Aktiengesellschaft

    发明人： LILLIE, Frank

    IPC分类号： H03L7/16 ,  H03B21/01

    CPC分类号： H03C3/0983 ,  H03C3/0941 ,  H03C3/0966 ,  H03L7/16 ,  H03L7/22 ,  H03L2207/12

    摘要： The invention relates to a method for producing mobile radio signals using a DDS (12) (direct digital frequency synthesis) and a modulator (14), comprising the following steps: A) an intermediate frequency (fout-DDS) is produced by controlling the DDS (12) using a DDS control word (S) and a DDS clock pulse frequency (fclk-DDS), and B) the intermediate frequency (fout-DDS) is transformed into an emission frequency (fout-RF) of the mobile radio signals, using the modulator (14), according to a reference frequency (fref) of the modulator (14). According to the invention, the reference frequency (fref) of the modulator (14) is used as a DDS clock pulse frequency (fclk-DDS), said frequency being unmodified or divided by a division factor (N). In order to produce the intermediate frequency (fout-DDS), the DDS control word (S) is selected in such a way that it compensates fluctuations of the reference frequency (fref) of the modulator (14).

    Method and apparatus for frequency modulation
    69.
    发明公开
    Method and apparatus for frequency modulation 有权
    Verfahren und Einrichtung zur Frequenzmodulation

    公开(公告)号：EP1345375A2

    公开(公告)日：2003-09-17

    申请号：EP03005251.8

    申请日：2003-03-10

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Adachi, Hisashi ,  Sakakura, Makoto

    IPC分类号： H04L27/12

    CPC分类号： H03C3/0966 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03L7/1976 ,  H03M7/3022 ,  H03M7/3037 ,  H03M7/304 ,  H04L27/12

    摘要： A voltage controlled oscillator (1), a variable frequency divider (2), a phase comparator (3), and a loop filter (4) form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part (M2) of the frequency division factor data with modulation data (X) by using an output signal of the variable frequency divider (2) as a clock. An output signal of the sigma-delta modulator (5) is added to an integral part (M1) of the frequency division factor data, and the resultant data becomes effective frequency division factor data (13) of the variable frequency divider (2). An output signal of the sigma-delta modulator (5) also becomes control data (14) after passing through a D/A converter (6), a low-pass filter (7), and an amplitude adjustment circuit (8). The control data (14) is inputted into a frequency modulation terminal of the voltage controlled oscillator (1). Therefore, it is possible to provide a frequency modulator that can use a reference signal source having no frequency modulation function, and perform modulation over a wide range of frequencies based on a digital modulation signal.

    摘要翻译： 压控振荡器（1），可变分频器（2），相位比较器（3）和环路滤波器（4）形成锁相环（PLL）。 Σ-Δ调制器5σ-Δ调制通过使用可变分频器（2）的输出信号作为时钟将分频因子数据的分数部分（M2）与调制数据（X）相加获得的数据。 Σ-Δ调制器（5）的输出信号被加到分频因子数据的整数部分（M1），并且所得数据成为可变分频器（2）的有效分频系数数据（13）。 Σ-Δ调制器（5）的输出信号在通过D / A转换器（6），低通滤波器（7）和振幅调整电路（8）之后也成为控制数据（14）。 控制数据（14）被输入到压控振荡器（1）的调频端子。 因此，可以提供一种可以使用不具有频率调制功能的参考信号源的频率调制器，并且可以基于数字调制信号在宽范围的频率上进行调制。